diff options
author | Aaron Durbin <adurbin@chromium.org> | 2016-07-26 11:48:06 -0500 |
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committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-27 21:25:06 +0200 |
commit | 139314bffd5ff29847661c536130d8d8d3e261bf (patch) | |
tree | 964701ca27fcf8ad741641b984c797986d60d261 /src/mainboard/google/bolt/chromeos.c | |
parent | 60cc75df83f2da64132b6da6dd431417da6b2f4e (diff) | |
download | coreboot-139314bffd5ff29847661c536130d8d8d3e261bf.tar.xz |
mainboard/google/bolt: remove unobtainable mainboard
The bolt board was a proof of concept device that has never
made it out in the wild. Moreover, I don't think any of these
boards exist any longer.
Change-Id: I5ca055d448659a2b8e2eafcfc2114a6b8f8a56a4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15901
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/bolt/chromeos.c')
-rw-r--r-- | src/mainboard/google/bolt/chromeos.c | 91 |
1 files changed, 0 insertions, 91 deletions
diff --git a/src/mainboard/google/bolt/chromeos.c b/src/mainboard/google/bolt/chromeos.c deleted file mode 100644 index 4bf2a784f2..0000000000 --- a/src/mainboard/google/bolt/chromeos.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <bootmode.h> -#include <arch/io.h> -#include <device/device.h> -#include <device/pci.h> -#include <southbridge/intel/lynxpoint/pch.h> -#include <southbridge/intel/common/gpio.h> - -#if CONFIG_EC_GOOGLE_CHROMEEC -#include "ec.h" -#include <ec/google/chromeec/ec.h> -#endif - -/* SPI Write protect is GPIO 16 */ -#define CROS_WP_GPIO 16 - -#ifndef __PRE_RAM__ -#include <boot/coreboot_tables.h> - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - struct lb_gpio chromeos_gpios[] = { - {CROS_WP_GPIO, ACTIVE_HIGH, 0, "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, - {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, - {-1, ACTIVE_HIGH, 0, "power"}, - {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - }; - lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -} -#endif - -int get_lid_switch(void) -{ -#if CONFIG_EC_GOOGLE_CHROMEEC - u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES); - - return !!(ec_switches & EC_SWITCH_LID_OPEN); -#else - return 0; -#endif -} - -/* The dev-switch is virtual */ -int get_developer_mode_switch(void) -{ - return 0; -} - -/* There are actually two recovery switches. One is the magic keyboard chord, - * the other is driven by Servo. */ -int get_recovery_mode_switch(void) -{ -#if CONFIG_EC_GOOGLE_CHROMEEC - u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES); - u32 ec_events; - - /* If a switch is set, we don't need to look at events. */ - if (ec_switches & (EC_SWITCH_DEDICATED_RECOVERY)) - return 1; - - /* Else check if the EC has posted the keyboard recovery event. */ - ec_events = google_chromeec_get_events_b(); - - return !!(ec_events & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); -#else - return 0; -#endif -} - -int get_write_protect_state(void) -{ - return get_gpio(CROS_WP_GPIO); -} |