diff options
author | Stefan Reinauer <reinauer@chromium.org> | 2013-02-11 11:11:36 -0800 |
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committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-02-11 22:02:32 +0100 |
commit | d7bd4eb003f5b6a13943418ae0ac53248a2e34d2 (patch) | |
tree | 716dbd6e38b118f369c73dcfed56216b3af42a6a /src/mainboard/google/butterfly/mainboard_smi.c | |
parent | 4815913968a1077fa7e56d8ec226a9cf18c80ea9 (diff) | |
download | coreboot-d7bd4eb003f5b6a13943418ae0ac53248a2e34d2.tar.xz |
Add support for "Butterfly" Chromebook
We're happy to announce coreboot support for the "Butterfly"
Chromebook, a.k.a HP Pavilion Chromebook.
More information at:
http://www.google.com/intl/en/chrome/devices/hp-pavilion-chromebook.html
This commit also includes support for the ENE KB3940Q embedded controller
running on Quanta's firmware.
Change-Id: I194f847a94005218ec04eeba091c3257ac459510
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2359
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/google/butterfly/mainboard_smi.c')
-rw-r--r-- | src/mainboard/google/butterfly/mainboard_smi.c | 115 |
1 files changed, 115 insertions, 0 deletions
diff --git a/src/mainboard/google/butterfly/mainboard_smi.c b/src/mainboard/google/butterfly/mainboard_smi.c new file mode 100644 index 0000000000..4e02a3cd7f --- /dev/null +++ b/src/mainboard/google/butterfly/mainboard_smi.c @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/bd82x6x/nvs.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/me.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <cpu/intel/model_206ax/model_206ax.h> + +/* Include EC functions */ +#include <ec/quanta/ene_kb3940q/ec.h> +#include "ec.h" + +int mainboard_io_trap_handler(int smif) +{ + printk(BIOS_DEBUG, "mainboard_io_trap_handler: %x\n", smif); + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + smm_get_gnvs()->smif = 0; + break; + default: + return 0; + } + + /* On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //gnvs->smif = 0; + return 1; +} + +void mainboard_smi_gpi(u16 gpi_sts) +{ + printk(BIOS_DEBUG, "warn: unknown mainboard_smi_gpi: %x\n", gpi_sts); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + printk(BIOS_DEBUG, "mainboard_smi_sleep: %x\n", slp_typ); + + /* Tell the EC to Enable USB power for S3 if requested */ + if (smm_get_gnvs()->s3u0 != 0 || smm_get_gnvs()->s3u1 != 0) + ec_mem_write(EC_EC_PSW, ec_mem_read(EC_EC_PSW) | EC_PSW_USB); + + /* Disable wake on USB, LAN & RTC */ + /* Enable Wake from Keyboard */ + if ((slp_typ == 4) || (slp_typ == 5)) { + printk(BIOS_DEBUG, "Disabling wake on RTC\n"); + ec_mem_write(EC_EC_PSW, EC_PSW_IKB); + } +} + +#define APMC_FINALIZE 0xcb +#define APMC_ACPI_EN 0xe1 +#define APMC_ACPI_DIS 0x1e + +static int mainboard_finalized = 0; + +int mainboard_smi_apmc(u8 apmc) +{ + printk(BIOS_DEBUG, "mainboard_smi_apmc: %x\n", apmc); + switch (apmc) { + case APMC_FINALIZE: + printk(BIOS_DEBUG, "APMC: FINALIZE\n"); + if (mainboard_finalized) { + printk(BIOS_DEBUG, "APMC#: Already finalized\n"); + return 0; + } + + intel_me_finalize_smm(); + intel_pch_finalize_smm(); + intel_sandybridge_finalize_smm(); + intel_model_206ax_finalize_smm(); + + mainboard_finalized = 1; + break; + + case APMC_ACPI_EN: + printk(BIOS_DEBUG, "APMC: ACPI_EN\n"); + /* Clear all pending events and enable SCI */ + ec_write_cmd(EC_CMD_ENABLE_ACPI_MODE); + break; + + case APMC_ACPI_DIS: + printk(BIOS_DEBUG, "APMC: ACPI_DIS\n"); + /* Clear all pending events and tell the EC that ACPI is disabled */ + ec_write_cmd(EC_CMD_DISABLE_ACPI_MODE); + break; + } + return 0; +} |