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authorBarnali Sarkar <barnali.sarkar@intel.com>2015-12-18 16:29:59 +0530
committerPatrick Georgi <pgeorgi@google.com>2016-01-19 16:21:29 +0100
commit497ff3ce7ce91d0d58ea60f58ad70422cb0ff2b8 (patch)
tree1485377c779cab27f1cd7bb95dfc408cc5a9547b /src/mainboard/google/chell/devicetree.cb
parent8bd6bd26eda8eefd9b87a3a0572af27f75360b9a (diff)
downloadcoreboot-497ff3ce7ce91d0d58ea60f58ad70422cb0ff2b8.tar.xz
google/chell: Enable FspSkipMpInit token
MP init is already handled in coreboot, but it is also part of FSP FSP has a implemented a provision to allow FSP to skip MP init and let coreboot handle it. BRANCH=none BUG=chrome-os-partner:44805 TEST=none CQ-DEPEND=CL:319353 Change-Id: I22c1add182b299e2ad9d413bc13c5a5acc6a3179 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ccf89c9d1fe18b74c385e7d12a6aef5b63d7b243 Original-Change-Id: I53b754fd10a140588ad67d9292d9bc04a6d43677 Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319194 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13000 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/chell/devicetree.cb')
-rw-r--r--src/mainboard/google/chell/devicetree.cb1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb
index f43d6c8383..81df06f083 100644
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@@ -43,6 +43,7 @@ chip soc/intel/skylake
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
+ register "FspSkipMpInit" = "1"
# VR Settings Configuration for 5 Domains
#+----------------+-------+-------+-------------+-------------+-------+