diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2015-10-09 09:25:32 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-10-27 15:17:17 +0100 |
| commit | f16bb7cce3767756e76b98d4f71fe3fe517a698d (patch) | |
| tree | a1d7b96fce53aa8ad50bd05882e993b44d6fa61c /src/mainboard/google/chell/devicetree.cb | |
| parent | 09170f16a4d5ce835d0652db0cc0051eb8b6ac89 (diff) | |
| download | coreboot-f16bb7cce3767756e76b98d4f71fe3fe517a698d.tar.xz | |
google/chell: Add new mainboard for chell
This is based on glados with minor changes:
- updated GPIOs based on schematic
- add _PRW for trackpad wake now that it is on a new GPIO
- add SPD for new memory config
- disable ALS
BUG=chrome-os-partner:46289
BRANCH=none
TEST=emerge-chell coreboot
Change-Id: Id5746bf2b5b26000fcc3f029b901bfe29b788dac
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9c5ebe98cf599ba80aac5e9ef238b7996789a819
Original-Change-Id: I75efda64a50b0e6e4a5c9008ce05d76c1e605b0c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/304927
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12151
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/chell/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/chell/devicetree.cb | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index 797865ddc8..5701dafa5b 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -54,16 +54,16 @@ chip soc/intel/skylake register "PcieRpClkReqNumber[4]" = "2" register "PortUsb20Enable[0]" = "1" # Type-C Port 1 - register "PortUsb20Enable[1]" = "1" # Type-C Port 2 - register "PortUsb20Enable[2]" = "1" # Bluetooth - register "PortUsb20Enable[4]" = "1" # Type-A Port 1 - register "PortUsb20Enable[6]" = "1" # Camera - register "PortUsb20Enable[8]" = "1" # Type-A Port 2 + register "PortUsb20Enable[1]" = "1" # Type-A Port + register "PortUsb20Enable[2]" = "1" # Camera + register "PortUsb20Enable[3]" = "1" # Bluetooth + register "PortUsb20Enable[4]" = "1" # SD + register "PortUsb20Enable[5]" = "1" # Type-C Port 2 register "PortUsb30Enable[0]" = "1" # Type-C Port 1 register "PortUsb30Enable[1]" = "1" # Type-C Port 2 - register "PortUsb30Enable[2]" = "1" # Type-A Port 1 - register "PortUsb30Enable[3]" = "1" # Type-A Port 2 + register "PortUsb30Enable[2]" = "1" # Type-A Port + register "PortUsb30Enable[3]" = "1" # SD # USB Per Port HS Preemphasis Bias register "Usb2AfePetxiset" = "{ 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, \ |