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authorDuncan Laurie <dlaurie@chromium.org>2016-06-06 17:13:42 -0700
committerDuncan Laurie <dlaurie@chromium.org>2016-06-09 17:07:26 +0200
commit7f3156dad67ad35f02afedd85cdf4a19e3c0875e (patch)
tree4584c4d6f24327279abf6de0864e0daffdf3fe48 /src/mainboard/google/chell
parent205ed2d2b58f9b93c7c665002aef0c775e64cf63 (diff)
downloadcoreboot-7f3156dad67ad35f02afedd85cdf4a19e3c0875e.tar.xz
skylake: gpio: Add support for setting 1.8V tolerant
Add the voltage tolerance GPIO attribute for configuring I2C/I2S buses that are at 1.8V. This is currently done by passing in a value to FSP but it is needed earlier than FSP if the I2C bus is used in verstage. This does not remove the need for the FSP input parameter, that is still required so FSP doesn't disable what has been set in coreboot. The mainboards that are affected are updated in this commit. This was tested by exercising I2C transactions to the 1.8V codec while in verstage on the google/chell mainboard. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I93d22c2e3bc0617c87f03c37a8746e22a112cc9c Reviewed-on: https://review.coreboot.org/15103 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/google/chell')
-rw-r--r--src/mainboard/google/chell/gpio.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/chell/gpio.h b/src/mainboard/google/chell/gpio.h
index 05897eb45a..6f30e1e849 100644
--- a/src/mainboard/google/chell/gpio.h
+++ b/src/mainboard/google/chell/gpio.h
@@ -192,8 +192,8 @@ static const struct pad_config gpio_table[] = {
/* I2C2_SCL */ PAD_CFG_NC(GPP_F5),
/* I2C3_SDA */ PAD_CFG_NC(GPP_F6),
/* I2C3_SCL */ PAD_CFG_NC(GPP_F7),
-/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* AUDIO1V8_SDA */
-/* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* AUDIO1V8_SCL */
+/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* AUDIO1V8_SDA */
+/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* AUDIO1V8_SCL */
/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */
/* I2C5_SCL */ PAD_CFG_GPO(GPP_F11, 0, DEEP),
/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),