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authorRizwan Qureshi <rizwan.qureshi@intel.com>2016-02-24 14:56:32 +0530
committerPatrick Georgi <pgeorgi@google.com>2016-03-12 09:21:20 +0100
commit898e965abb64044dd432563af4d9de2c50d9f718 (patch)
treeed8c8d8fb99bd172f1a0724497c10bc2fb0a13a7 /src/mainboard/google/chell
parentaf31a998c95f377e65798b8fdae1e303f67de45d (diff)
downloadcoreboot-898e965abb64044dd432563af4d9de2c50d9f718.tar.xz
glados/chell: send an extra VR mailbox command
MPS IMVP8 VR is not entering PS4 in S0ix on Glados/Chell. The pcode has been updated since v76, and it requires an an extra VR mailbox command should be sent from coreboot to pcode. BUG=chrome-os-partner:48511 BRANCH=None TEST=Verified on glados, clean S0ix entry and exit. IMVP8 power is also pretty low CQ-DEPEND=CL:329393 Change-Id: Ia3ef4031269ac2d4557bba65de34c41a8d73f89a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3e66903c9017f9d3f45c97b68284f4e1058c03e2 Original-Change-Id: Ie9e370556bb35d02f6bfcfe5cb81dd977fceace1 Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/329480 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13983 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/chell')
-rw-r--r--src/mainboard/google/chell/devicetree.cb15
1 files changed, 9 insertions, 6 deletions
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb
index bb925cebe1..428779a470 100644
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@@ -63,7 +63,7 @@ chip soc/intel/skylake
#| Psi2Threshold | 4A | 5A | 5A | 5A | 5A |
#| Psi3Threshold | 1A | 1A | 1A | 1A | 1A |
#| Psi3Enable | 1 | 1 | 1 | 1 | 1 |
- #| Psi4Enable | 0 | 0 | 0 | 0 | 0 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 | 1 |
#| ImonSlope | 0 | 0 | 0 | 0 | 0 |
#| ImonOffset | 0 | 0 | 0 | 0 | 0 |
#| IccMax | 7A | 34A | 34A | 35A | 35A |
@@ -75,7 +75,7 @@ chip soc/intel/skylake
.psi2threshold = VR_CFG_AMP(4),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
- .psi4enable = 0,
+ .psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(7),
@@ -88,7 +88,7 @@ chip soc/intel/skylake
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
- .psi4enable = 0,
+ .psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(34),
@@ -101,7 +101,7 @@ chip soc/intel/skylake
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
- .psi4enable = 0,
+ .psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(34),
@@ -114,7 +114,7 @@ chip soc/intel/skylake
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
- .psi4enable = 0,
+ .psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(35),
@@ -127,7 +127,7 @@ chip soc/intel/skylake
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
- .psi4enable = 0,
+ .psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(35),
@@ -174,6 +174,9 @@ chip soc/intel/skylake
# PL2 override 15W
register "tdp_pl2_override" = "15"
+ # Send an extra VR mailbox command for the supported MPS IMVP8 model
+ register "SendVrMbxCmd" = "1"
+
device cpu_cluster 0 on
device lapic 0 on end
end