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authorYidi Lin <yidi.lin@mediatek.com>2021-04-12 12:01:48 +0800
committerHung-Te Lin <hungte@chromium.org>2021-04-14 00:55:47 +0000
commit97b9d9ef246b29043cb3b6da25ae09cbc4863815 (patch)
treeedefe328b01b204ec99657ba8233277ec5dcbf9a /src/mainboard/google/cherry/Makefile.inc
parentdf9549efb2649e492485a4cc2ff6c3c0b5ccc788 (diff)
downloadcoreboot-97b9d9ef246b29043cb3b6da25ae09cbc4863815.tar.xz
mb/google/cherry: Add MediaTek MT8195 reference board
TEST=boot from SPI-NOR and UART works fine. Change-Id: I279b3d2da8a30b38686005212f6c019a9a646874 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/mainboard/google/cherry/Makefile.inc')
-rw-r--r--src/mainboard/google/cherry/Makefile.inc13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/mainboard/google/cherry/Makefile.inc b/src/mainboard/google/cherry/Makefile.inc
new file mode 100644
index 0000000000..ada29aa0d1
--- /dev/null
+++ b/src/mainboard/google/cherry/Makefile.inc
@@ -0,0 +1,13 @@
+bootblock-y += memlayout.ld
+bootblock-y += chromeos.c
+
+verstage-y += memlayout.ld
+verstage-y += chromeos.c
+verstage-y += reset.c
+
+romstage-y += memlayout.ld
+romstage-y += chromeos.c
+
+ramstage-y += memlayout.ld
+ramstage-y += chromeos.c
+ramstage-y += reset.c