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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2018-09-24 13:17:40 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-09-26 15:37:55 +0000 |
| commit | cc16ec13ef17cd216df44ab7fccd786238a0ea20 (patch) | |
| tree | 0123c11ecad90d19366b1559e900745e9e979bae /src/mainboard/google/cheza/chromeos.fmd | |
| parent | dfaff4d18a711f764c9198f488435fdc553dcea2 (diff) | |
| download | coreboot-cc16ec13ef17cd216df44ab7fccd786238a0ea20.tar.xz | |
src/mainboard/pcengines/apu2/Kconfig: Clean up PINMUX settings
Configuration of pins exposed by superIO are inconsistent between board
variants. Each platform should have UARTs enabled, this is expected
behaviour of these pins. Given that APU2_PINMUX_UART_x can be set for
all boards as default.
Change-Id: Ifb7dfe23a95ba0e572adc38212333d9fdd234d53
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/28720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/cheza/chromeos.fmd')
0 files changed, 0 insertions, 0 deletions