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authorMatt DeVillier <matt.devillier@gmail.com>2017-08-20 17:56:48 -0500
committerMartin Roth <martinroth@google.com>2017-09-16 22:31:32 +0000
commit4f20a4ae47492fc86293f1c6aed063177992fbaf (patch)
tree0fdb68c963612f0b4cbc901efbf04293719b9ea2 /src/mainboard/google/cyan/acpi
parent7427abce07fb80289646b7653242022182b9e8f9 (diff)
downloadcoreboot-4f20a4ae47492fc86293f1c6aed063177992fbaf.tar.xz
google/edgar: add new board as variant of cyan baseboard
Add support for google/edgar (Acer Chromebook 14 CB3-431) as a variant of the cyan Braswell basebaseboard. - Add board-specific code as the new edgar variant - Add common code to the baseboard which will apply to all variants other than cyan Sourced from Chromium branch firmware-edgar-7287.167.B, commit 2319742: Edgar: Add Micron MT52L256M32D1PF-107 SPD data Change-Id: I58548cbbc85828f37c0023e8aa9e09bdca612659 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/cyan/acpi')
-rw-r--r--src/mainboard/google/cyan/acpi/codec_realtek.asl63
1 files changed, 63 insertions, 0 deletions
diff --git a/src/mainboard/google/cyan/acpi/codec_realtek.asl b/src/mainboard/google/cyan/acpi/codec_realtek.asl
new file mode 100644
index 0000000000..d3fa84eaa7
--- /dev/null
+++ b/src/mainboard/google/cyan/acpi/codec_realtek.asl
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB.PCI0.I2C5)
+{
+ /* Realtek Audio Codec */
+ Device (RTEK) /* Audio Codec driver I2C */
+ {
+ Name (_ADR, 0)
+ Name (_HID, AUDIO_CODEC_HID)
+ Name (_CID, AUDIO_CODEC_CID)
+ Name (_DDN, AUDIO_CODEC_DDN)
+ Name (_UID, 1)
+
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ Name(SBUF,ResourceTemplate ()
+ {
+ I2CSerialBus(
+ AUDIO_CODEC_I2C_ADDR, /* SlaveAddress: bus address */
+ ControllerInitiated, /* SlaveMode: default to ControllerInitiated */
+ 400000, /* ConnectionSpeed: in Hz */
+ AddressingMode7Bit, /* Addressing Mode: default to 7 bit */
+ "\\_SB.PCI0.I2C5", /* ResourceSource: I2C bus controller name */
+ )
+
+ /* Jack Detect (index 0) */
+ GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
+ "\\_SB.GPSW") { JACK_DETECT_GPIO_INDEX }
+ } )
+ Return (SBUF)
+ }
+
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+ }
+}
+
+Scope (\_SB.PCI0.LPEA)
+{
+ Name (GBUF, ResourceTemplate ()
+ {
+ /* Jack Detect (index 0) */
+ GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
+ "\\_SB.GPSW") { JACK_DETECT_GPIO_INDEX }
+ })
+}