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| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2019-09-02 15:01:56 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-09-09 13:30:10 +0000 |
| commit | aa8d7721d400c20b73a1de8036d45654bdc625ee (patch) | |
| tree | 7605139eb69fc2e1a8fc4dc38d9283a323b55670 /src/mainboard/google/cyan/ec.h | |
| parent | d6c2d1df2cbe190743fdd97d4fdabd33518db6a8 (diff) | |
| download | coreboot-aa8d7721d400c20b73a1de8036d45654bdc625ee.tar.xz | |
lib/spd_bin: Extend DDR4 spd information
From DDR4 SPD spec:
Byte 4 (0x004): SDRAM Density and Banks
Bits [7, 6]:
00 = 0 (no bank groups)
01 = 1 (2 bank groups)
10 = 2 (4 bank groups)
11 = reserved
Bit [5, 4] :
00 = 2 (4 banks)
01 = 3 (8 banks)
All others reserved
Separate DDR3 and DDR4 banks. And extened capmb, rows, cols and ranks.
Separate DDR3 and DDR4 ORGANIZATION/BUS_DEV_WIDTH offset.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I5f56975ce73d8ed2d4de7d9fd08e5ae86993e731
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/cyan/ec.h')
0 files changed, 0 insertions, 0 deletions