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authorRavi Sarawadi <ravishankar.sarawadi@intel.com>2015-09-09 14:12:16 -0700
committerMartin Roth <martinroth@google.com>2016-01-28 20:43:22 +0100
commitd077b58c61896c71218a90292bbcd5063c11698f (patch)
tree0d23442914cc3d1bcafae641d101f3683d9c3778 /src/mainboard/google/cyan/spd
parent9657f3bb097ef5506d66a999118a4157ddadf7d5 (diff)
downloadcoreboot-d077b58c61896c71218a90292bbcd5063c11698f.tar.xz
soc/braswell: Fix issues found during static code analysis
TEST=Build, boot to OS Original-Reviewed-on: https://chromium-review.googlesource.com/299483 Original-Reviewed-by: Aaron Durbin <adurbin@google.com> Change-Id: I738003b8dfff6a5255085d39e378e18d6ad36bcf Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/12738 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/cyan/spd')
-rw-r--r--src/mainboard/google/cyan/spd/spd.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c
index 31f6911be1..c2e9e79c3b 100644
--- a/src/mainboard/google/cyan/spd/spd.c
+++ b/src/mainboard/google/cyan/spd/spd.c
@@ -162,6 +162,9 @@ static void set_dimm_info(uint32_t chips, uint8_t *spd, struct dimm_info *dimm)
case 8:
log2_chips = 3;
break;
+
+ default:
+ log2_chips = 0;
}
dimm->bus_width = (uint8_t)(log2_chips + (spd[7] & 7) + 2 - 3);
}