soc/intel/braswell: add default option to use public FSP

The current Braswell FSP 1.1 header in vendorcode/intel, for
which there is no publicly available FSP binary, contains silicon
init UPDs which are not found in the publicly available header/binary
in the FSP Github repo. This prevents new boards from being added
which use the public Braswell FSP header/binary.

To resolve this, move the UPDs not found in the public header from
the soc's chip.c to ramstage.c for the boards which use them. Add
a Kconfig option to use the current non-public FSP header and
select it for boards which need it (google/cyan variants); set the
public FSP option as the default. Use the Kconfig option to set
FSP_HEADER_PATH to ensure the correct header is used.

Test: build google/cyan and intel/strago using non-public and
public FSP header/binaries respectively.

Change-Id: I43cf18b98c844175a87b61fdbe4b0b24484e5702
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>

2 files changed, 8 insertions, 7 deletions

diff --git a/src/mainboard/google/cyan/variants/relm/devicetree.cb b/src/mainboard/google/cyan/variants/relm/devicetree.cb
index 65e662c5dd..e1bbb0ac5b 100644
--- a/src/mainboard/google/cyan/variants/relm/devicetree.cb
+++ b/src/mainboard/google/cyan/variants/relm/devicetree.cb
@@ -80,13 +80,6 @@ chip soc/intel/braswell
 	register "I2C5Frequency" = "1"
 	register "I2C6Frequency" = "1"
 
-	# Follow Intel recommendation to set BSW D-stepping PERPORTRXISET 2 (low strength)
-	register "D0Usb2Port0PerPortRXISet" = "2"
-	register "D0Usb2Port1PerPortRXISet" = "2"
-	register "D0Usb2Port2PerPortRXISet" = "2"
-	register "D0Usb2Port3PerPortRXISet" = "2"
-	register "D0Usb2Port4PerPortRXISet" = "2"
-
 	# LPE audio codec settings
 	register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
 
diff --git a/src/mainboard/google/cyan/variants/relm/ramstage.c b/src/mainboard/google/cyan/variants/relm/ramstage.c
index 27f9dfa241..3fbd2aebd9 100644
--- a/src/mainboard/google/cyan/variants/relm/ramstage.c
+++ b/src/mainboard/google/cyan/variants/relm/ramstage.c
@@ -36,5 +36,13 @@ void board_silicon_USB2_override(SILICON_INIT_UPD *params)
 		params->Usb2Port3PerPortTxiSet = 0;
 		params->Usb2Port3IUsbTxEmphasisEn = 2;
 		params->Usb2Port3PerPortTxPeHalf = 1;
+
+		//Follow Intel recommendation to set
+		//BSW D-stepping PERPORTRXISET 2 (low strength)
+		params->D0Usb2Port0PerPortRXISet = 2;
+		params->D0Usb2Port1PerPortRXISet = 2;
+		params->D0Usb2Port2PerPortRXISet = 2;
+		params->D0Usb2Port3PerPortRXISet = 2;
+		params->D0Usb2Port4PerPortRXISet = 2;
 	}
 }