google/setzer: add new board as variant of cyan baseboard

Add support for google/setzer (HP Chromebook 11 G5) as
a variant of the cyan Braswell baseboard.

- Add board-specific code as the new setzer variant
- Add new I2C touchscreen device and SPD files to the baseboard
for potential reuse by other variants

Sourced from Chromium branch firmware-strago-7287.B,
commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF)

Change-Id: Ibcebebeb469c4bd6139b8ce83a1ca5ca560c2252
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 45 insertions, 0 deletions

diff --git a/src/mainboard/google/cyan/variants/setzer/ramstage.c b/src/mainboard/google/cyan/variants/setzer/ramstage.c
new file mode 100644
index 0000000000..38bc34cb35
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/setzer/ramstage.c
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/ramstage.h>
+
+void board_silicon_USB2_override(SILICON_INIT_UPD *params)
+{
+	if (SocStepping() >= SocD0) {
+		/* Left External Port*/
+		params->Usb2Port1PerPortPeTxiSet = 7;
+		params->Usb2Port1PerPortTxiSet = 6;
+		params->Usb2Port1IUsbTxEmphasisEn = 3;
+		params->Usb2Port1PerPortTxPeHalf = 1;
+
+		/* Right External Port */
+		params->Usb2Port2PerPortPeTxiSet = 7;
+		params->Usb2Port2PerPortTxiSet = 6;
+		params->Usb2Port2IUsbTxEmphasisEn = 3;
+		params->Usb2Port2PerPortTxPeHalf = 1;
+
+		/* Camera*/
+		params->Usb2Port3PerPortPeTxiSet = 7;
+		params->Usb2Port3PerPortTxiSet = 6;
+		params->Usb2Port3IUsbTxEmphasisEn = 3;
+		params->Usb2Port3PerPortTxPeHalf = 1;
+
+		/* BT */
+		params->Usb2Port4PerPortPeTxiSet = 7;
+		params->Usb2Port4PerPortTxiSet = 6;
+		params->Usb2Port4IUsbTxEmphasisEn = 3;
+		params->Usb2Port4PerPortTxPeHalf = 1;
+	}
+}