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author | Matt DeVillier <matt.devillier@gmail.com> | 2017-08-24 16:31:41 -0500 |
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committer | Martin Roth <martinroth@google.com> | 2017-09-21 17:31:21 +0000 |
commit | 2f7813f7b3668e67e1ffa7675e53156089a568ef (patch) | |
tree | 2580a77ce734621df3fcb77f38571afad91e95f5 /src/mainboard/google/cyan/variants/terra/include/variant/onboard.h | |
parent | cd935e678a8b12cae0827c438a9c86489e6acee3 (diff) | |
download | coreboot-2f7813f7b3668e67e1ffa7675e53156089a568ef.tar.xz |
google/terra: add new board as variant of cyan baseboard
Add support for google/terra (Asus Chromebook C202SA/C300SA) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new terra variant
- Add code to the baseboard to handle terra's unique thermal management
- Add new shared SPD files to baseboard
Sourced from Chromium branch firmware-terra-7287.154.B,
commit 153f08a: Revert "Revert "soc/intel/braswell: Populate NVS SCC BAR1""
Change-Id: Ib2682eda15a989f2ec20c78317561f5b6a97483a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/cyan/variants/terra/include/variant/onboard.h')
-rw-r--r-- | src/mainboard/google/cyan/variants/terra/include/variant/onboard.h | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/onboard.h b/src/mainboard/google/cyan/variants/terra/include/variant/onboard.h new file mode 100644 index 0000000000..613039b98f --- /dev/null +++ b/src/mainboard/google/cyan/variants/terra/include/variant/onboard.h @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/cyan/irqroute.h> + +/* + * Calculation of gpio based irq. + * Gpio banks ordering : GPSW, GPNC, GPEC, GPSE + * Max direct irq (MAX_DIRECT_IRQ) is 114. + * Size of gpio banks are + * GPSW_SIZE = 98 + * GPNC_SIZE = 73 + * GPEC_SIZE = 27 + * GPSE_SIZE = 86 + */ + +/* KBD: Gpio index in N bank */ +#define BOARD_I8042_GPIO_INDEX 17 +/* Audio: Gpio index in SW bank */ +#define JACK_DETECT_GPIO_INDEX 95 +/* SCI: Gpio index in N bank */ +#define BOARD_SCI_GPIO_INDEX 15 +/* Trackpad: Gpio index in N bank */ +#define BOARD_TRACKPAD_GPIO_INDEX 18 + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 5 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +/* SD CARD gpio */ +#define SDCARD_CD 81 + +#define AUDIO_CODEC_HID "10EC5650" +#define AUDIO_CODEC_CID "10EC5650" +#define AUDIO_CODEC_DDN "RTEK Codec Controller" +#define AUDIO_CODEC_I2C_ADDR 0x1A + +#define TERRA2_PROJECT_ID 0x00 + +#define DPTF_TERRA2_CPU_PASSIVE 80 +#define DPTF_TERRA2_CPU_CRITICAL 90 +#define DPTF_TERRA3_CPU_PASSIVE 80 +#define DPTF_TERRA3_CPU_CRITICAL 90 + +/* I2C data hold time */ +#define BOARD_I2C5_DATA_HOLD_TIME 0x1E +#define BOARD_I2C6_DATA_HOLD_TIME 0x1E + +#endif |