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author | Matt DeVillier <matt.devillier@gmail.com> | 2017-08-24 16:31:41 -0500 |
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committer | Martin Roth <martinroth@google.com> | 2017-09-21 17:31:21 +0000 |
commit | 2f7813f7b3668e67e1ffa7675e53156089a568ef (patch) | |
tree | 2580a77ce734621df3fcb77f38571afad91e95f5 /src/mainboard/google/cyan/variants/terra/romstage.c | |
parent | cd935e678a8b12cae0827c438a9c86489e6acee3 (diff) | |
download | coreboot-2f7813f7b3668e67e1ffa7675e53156089a568ef.tar.xz |
google/terra: add new board as variant of cyan baseboard
Add support for google/terra (Asus Chromebook C202SA/C300SA) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new terra variant
- Add code to the baseboard to handle terra's unique thermal management
- Add new shared SPD files to baseboard
Sourced from Chromium branch firmware-terra-7287.154.B,
commit 153f08a: Revert "Revert "soc/intel/braswell: Populate NVS SCC BAR1""
Change-Id: Ib2682eda15a989f2ec20c78317561f5b6a97483a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/cyan/variants/terra/romstage.c')
-rw-r--r-- | src/mainboard/google/cyan/variants/terra/romstage.c | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/src/mainboard/google/cyan/variants/terra/romstage.c b/src/mainboard/google/cyan/variants/terra/romstage.c new file mode 100644 index 0000000000..e670461ff8 --- /dev/null +++ b/src/mainboard/google/cyan/variants/terra/romstage.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> +#include <chip.h> +#include <mainboard/google/cyan/spd/spd_util.h> + +void mainboard_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *memory_params) +{ + int ram_id = get_ramid(); + + /* + * RAMID = 3 - 2GiB Micron MT52L256M32D1PF-107 + * RAMID = 11 - 4GiB Micron MT52L256M32D1PF-107 + */ + if (ram_id == 3 || ram_id == 11) { + + /* + * For new micron part, it requires read/receive + * enable training before sending cmds to get MR8. + * To override dram geometry settings as below: + * + * PcdDramWidth = x32 + * PcdDramDensity = 8Gb + * PcdDualRankDram = disable + */ + memory_params->PcdRxOdtLimitChannel0 = 1; + memory_params->PcdRxOdtLimitChannel1 = 1; + memory_params->PcdDisableAutoDetectDram = 1; + memory_params->PcdDramWidth = 2; + memory_params->PcdDramDensity = 3; + memory_params->PcdDualRankDram = 0; + } + + /* Update SPD data */ + memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; + memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0; + memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config; + memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config; +} |