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authorfdurairx <felixx.durairaj@intel.com>2015-08-21 15:36:53 -0700
committerMartin Roth <martinroth@google.com>2016-01-28 20:34:06 +0100
commitaff502e87ae57fa2dc09367d00f143b6befb9530 (patch)
tree53476f7b39033ed036b7a7bf784e2410c24d7381 /src/mainboard/google/cyan
parent71c60ca4821f9ebd51066b2fb4166fd974755666 (diff)
downloadcoreboot-aff502e87ae57fa2dc09367d00f143b6befb9530.tar.xz
soc/braswell: Fix DSP clock
The codec clock frequency was incorrectly set to 25MHz. The only available frequency is 19.2MHz through external clock and PLL. Original-Reviewed-on: https://chromium-review.googlesource.com/295768 Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I9bef334a5a3aaee28fcc4937180896ff49969bc5 Signed-off-by: Felix Durairaj <felixx.durairaj@intel.com> Reviewed-on: https://review.coreboot.org/12732 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/cyan')
-rwxr-xr-xsrc/mainboard/google/cyan/devicetree.cb3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb
index c36ae3d235..8932cf4391 100755
--- a/src/mainboard/google/cyan/devicetree.cb
+++ b/src/mainboard/google/cyan/devicetree.cb
@@ -72,8 +72,7 @@ chip soc/intel/braswell
register "ISPPciDevConfig" = "3"
# LPE audio codec settings
- register "lpe_codec_clk_freq" = "25" # 25MHz clock
- register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
+ register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
# Enable devices in ACPI mode
register "lpss_acpi_mode" = "1"