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| author | Christian Walter <christian.walter@9elements.com> | 2019-12-18 15:07:59 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-03-23 16:54:58 +0000 |
| commit | be3979c873d23cb0543e635bba59bd85ab67fed0 (patch) | |
| tree | c8a1064696607573eebd0b03c411a8aa090f015c /src/mainboard/google/cyan | |
| parent | 09eb8d0c9b3b9e7b765520114d148a19926ff886 (diff) | |
| download | coreboot-be3979c873d23cb0543e635bba59bd85ab67fed0.tar.xz | |
acpi: Change Processor ACPI Name (Intel only)
The ACPI Spec 2.0 states, that Processor declarations should be made
within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated
and is removed here for Intel CPUs only.
Tested on:
* X11SSH (Kabylake)
* CFL Platform
* Asus P8Z77-V LX2 and Windows 10
FWTS does not return FAIL anymore on ACPI tests
Tested-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: Ib101ed718f90f9056d2ecbc31b13b749ed1fc438
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/google/cyan')
| -rw-r--r-- | src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl index bdd9792e8c..49991a8435 100644 --- a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl +++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl @@ -41,11 +41,11 @@ #define DPTF_CPU_ACTIVE_AC4 50 #endif -External (\_PR.CP00._TSS, MethodObj) -External (\_PR.CP00._TPC, MethodObj) -External (\_PR.CP00._PTC, PkgObj) -External (\_PR.CP00._TSD, PkgObj) -External (\_PR.CP00._PSS, MethodObj) +External (\_SB.CP00._TSS, MethodObj) +External (\_SB.CP00._TPC, MethodObj) +External (\_SB.CP00._PTC, PkgObj) +External (\_SB.CP00._TSD, PkgObj) +External (\_SB.CP00._PSS, MethodObj) Device (B0DB) { @@ -66,8 +66,8 @@ Device (B0DB) Method (_TSS) { - If (CondRefOf (\_PR.CP00._TSS)) { - Return (\_PR.CP00._TSS) + If (CondRefOf (\_SB.CP00._TSS)) { + Return (\_SB.CP00._TSS) } Else { Return (Package () { @@ -78,8 +78,8 @@ Device (B0DB) Method (_TPC) { - If (CondRefOf (\_PR.CP00._TPC)) { - Return (\_PR.CP00._TPC) + If (CondRefOf (\_SB.CP00._TPC)) { + Return (\_SB.CP00._TPC) } Else { Return (0) } @@ -87,8 +87,8 @@ Device (B0DB) Method (_PTC) { - If (CondRefOf (\_PR.CP00._PTC)) { - Return (\_PR.CP00._PTC) + If (CondRefOf (\_SB.CP00._PTC)) { + Return (\_SB.CP00._PTC) } Else { Return (Package () { @@ -100,8 +100,8 @@ Device (B0DB) Method (_TSD) { - If (CondRefOf (\_PR.CP00._TSD)) { - Return (\_PR.CP00._TSD) + If (CondRefOf (\_SB.CP00._TSD)) { + Return (\_SB.CP00._TSD) } Else { Return (Package () { @@ -112,8 +112,8 @@ Device (B0DB) Method (_TDL) { - If (CondRefOf (\_PR.CP00._TSS)) { - Store (SizeOf (\_PR.CP00._TSS ()), Local0) + If (CondRefOf (\_SB.CP00._TSS)) { + Store (SizeOf (\_SB.CP00._TSS ()), Local0) Decrement (Local0) Return (Local0) } Else { @@ -140,8 +140,8 @@ Device (B0DB) Method (_PSS) { - If (CondRefOf (\_PR.CP00._PSS)) { - Return (\_PR.CP00._PSS) + If (CondRefOf (\_SB.CP00._PSS)) { + Return (\_SB.CP00._PSS) } Else { Return (Package () { @@ -155,8 +155,8 @@ Device (B0DB) /* Check for mainboard specific _PDL override */ If (CondRefOf (\_SB.MPDL)) { Return (\_SB.MPDL) - } ElseIf (CondRefOf (\_PR.CP00._PSS)) { - Store (SizeOf (\_PR.CP00._PSS ()), Local0) + } ElseIf (CondRefOf (\_SB.CP00._PSS)) { + Store (SizeOf (\_SB.CP00._PSS ()), Local0) Decrement (Local0) Return (Local0) } Else { |