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| author | Matt DeVillier <matt.devillier@gmail.com> | 2019-02-25 23:40:40 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-02-27 11:04:00 +0000 |
| commit | ce529b631819574c3e1f6b10e60725df1638013e (patch) | |
| tree | 72149507e54c8ff754936f9aa52e1bb7bd959593 /src/mainboard/google/cyan | |
| parent | 2201da3a8b9497792137bfa13cb47343efa5e42b (diff) | |
| download | coreboot-ce529b631819574c3e1f6b10e60725df1638013e.tar.xz | |
mb/google/cyan: fix RAM training on edgar variant
Adapted from Chromium commit 5351dc0d
[Edgar: To set the RX ODT limit and dram geometry with RAMID detection]
Several cyan variants require memory init parameters be passed to FSP
for handling of specific Micron modules; without these, RAM init will
fail when loading training data from the MRC cache, and boot will halt.
This was missed when I upstreamed edgar along with the other cyan
variants, so add the required memory init parameters for edgar as per
its source Chromium branch.
Test: build/boot on edgar board with affected Micron memory
modules, verify boot successful with populated MRC cache.
Change-Id: I6a2bc30b54ff1a17c854a90dfcb2308d27ee2be7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31615
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/cyan')
| -rw-r--r-- | src/mainboard/google/cyan/variants/edgar/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/mainboard/google/cyan/variants/edgar/romstage.c | 47 |
2 files changed, 48 insertions, 0 deletions
diff --git a/src/mainboard/google/cyan/variants/edgar/Makefile.inc b/src/mainboard/google/cyan/variants/edgar/Makefile.inc index 2e8b02c64e..ad9ac8a422 100644 --- a/src/mainboard/google/cyan/variants/edgar/Makefile.inc +++ b/src/mainboard/google/cyan/variants/edgar/Makefile.inc @@ -14,6 +14,7 @@ ## GNU General Public License for more details. ## +romstage-y += romstage.c romstage-y += spd_util.c ramstage-y += gpio.c diff --git a/src/mainboard/google/cyan/variants/edgar/romstage.c b/src/mainboard/google/cyan/variants/edgar/romstage.c new file mode 100644 index 0000000000..12fef77394 --- /dev/null +++ b/src/mainboard/google/cyan/variants/edgar/romstage.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> +#include <baseboard/variants.h> +#include <mainboard/google/cyan/spd/spd_util.h> + +void variant_memory_init_params(MEMORY_INIT_UPD *memory_params) +{ + int ram_id = get_ramid(); + + /* + * RAMID = 5 - 4GiB Micron MT52L256M32D1PF-107 + * RAMID = 7 - 2GiB Micron MT52L256M32D1PF-107 + */ + if (ram_id == 5 || ram_id == 7) { + + /* + * For new micron part, it requires read/receive + * enable training before sending cmds to get MR8. + * To override dram geometry settings as below: + * + * PcdDramWidth = x32 + * PcdDramDensity = 8Gb + * PcdDualRankDram = disable + */ + memory_params->PcdRxOdtLimitChannel0 = 1; + memory_params->PcdRxOdtLimitChannel1 = 1; + memory_params->PcdDisableAutoDetectDram = 1; + memory_params->PcdDramWidth = 2; + memory_params->PcdDramDensity = 3; + memory_params->PcdDualRankDram = 0; + } +} |