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| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2019-12-16 14:50:42 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-01-14 18:28:50 +0000 |
| commit | 7bc90bce36b4f907cd5d309a9fa11c46635d1194 (patch) | |
| tree | df0bba660bf6a6bcb3ff9831a15eeb37c95e1671 /src/mainboard/google/dedede/chromeos.fmd | |
| parent | 23140933b7d6bbe77e60c2d6a4b52ec7c48a2474 (diff) | |
| download | coreboot-7bc90bce36b4f907cd5d309a9fa11c46635d1194.tar.xz | |
mb/google/dedede: Add dedede mainboard
Add mainboard stubs for Dedede. More functionalities will be added later.
BUG=b:144768001
TEST=Build test.
Change-Id: I7e6cb8adaee7b6bb95e9a96f96466646a78bd0fc
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38277
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/dedede/chromeos.fmd')
| -rw-r--r-- | src/mainboard/google/dedede/chromeos.fmd | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/chromeos.fmd b/src/mainboard/google/dedede/chromeos.fmd new file mode 100644 index 0000000000..60ea3ded64 --- /dev/null +++ b/src/mainboard/google/dedede/chromeos.fmd @@ -0,0 +1,47 @@ +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x4ff000 + } + SI_BIOS@0x500000 0x1b00000 { + # Place RW_LEGACY at the start of BIOS region such that the rest + # of BIOS regions start at 16MiB boundary. Since this is a 32MiB + # SPI flash only the top 16MiB actually gets memory mapped. + RW_LEGACY(CBFS)@0x0 0xf00000 + RW_SECTION_A@0xf00000 0x3e0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x3cffc0 + RW_FWID_A@0x3dffc0 0x40 + } + RW_SECTION_B@0x12e0000 0x3e0000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x3cffc0 + RW_FWID_B@0x3dffc0 0x40 + } + RW_MISC@0x16c0000 0x40000 { + UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x20000 + } + RW_ELOG(PRESERVE)@0x30000 0x4000 + RW_SHARED@0x34000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x38000 0x2000 + RW_NVRAM(PRESERVE)@0x3a000 0x6000 + } + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO@0x1700000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 + } + } + } +} |