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author | Marco Chen <marcochen@chromium.org> | 2020-04-29 14:47:28 +0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-04 09:44:42 +0000 |
commit | 44e304abe11d87ba3bda7b566fe972aee96b159b (patch) | |
tree | e60cb6aa2a9a42ce03e11e8736cabaace04b2bb2 /src/mainboard/google/dedede/romstage.c | |
parent | bf59fac286653dc60f2279cd01194de729d3e789 (diff) | |
download | coreboot-44e304abe11d87ba3bda7b566fe972aee96b159b.tar.xz |
mb/google/dedede: Read DRAM part number from CBI
The index of MEM_STRAPS will be migrated from per DRAM part number to
per DRAM characteristic therefore one index mapped to a single SPD
binary can represent to multiple DRAM part numbers as long as their
characteristic is the same for DRAM controller to support. In this case,
the real DRAM part number would be provisioned in the CBI instead of SPD
in the factory flow. As a result, we need to extract DRAM part number
from CBI.
BUG=b:152019429
BRANCH=None
TEST=1. provision dram_part_num field of CBI
2. check DRAM part number is correct in SMBIOS for memory device
Change-Id: I40780a35e04efb279591e9db179cb86b5e907c0d
Signed-off-by: Marco Chen <marcochen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/mainboard/google/dedede/romstage.c')
-rw-r--r-- | src/mainboard/google/dedede/romstage.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/romstage.c b/src/mainboard/google/dedede/romstage.c index 7a700f4ff4..3155f70763 100644 --- a/src/mainboard/google/dedede/romstage.c +++ b/src/mainboard/google/dedede/romstage.c @@ -6,9 +6,13 @@ */ #include <baseboard/variants.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> #include <gpio.h> +#include <memory_info.h> #include <soc/meminit.h> #include <soc/romstage.h> +#include <string.h> #include <variant/gpio.h> void mainboard_memory_init_params(FSPM_UPD *memupd) @@ -22,3 +26,19 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated); } + +bool mainboard_get_dram_part_num(const char **part_num, size_t *len) +{ + static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; + + if (google_chromeec_cbi_get_dram_part_num(&part_num_store[0], + sizeof(part_num_store)) < 0) { + printk(BIOS_ERR, "No DRAM part number in CBI!\n"); + return false; + } + + + *part_num = &part_num_store[0]; + *len = strlen(part_num_store); + return true; +} |