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| author | Aamir Bohra <aamir.bohra@intel.com> | 2020-03-25 15:31:12 +0530 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-04-01 16:39:28 +0000 |
| commit | a23e0c9d74b7f06738ebf28b068e1bd63f246982 (patch) | |
| tree | 5afd6c3027ebca12e4d6f94b443fe42dd1f3b75e /src/mainboard/google/dedede/romstage.c | |
| parent | 51ce41c0e661fd9cb9207463bcbd920e55b44a62 (diff) | |
| download | coreboot-a23e0c9d74b7f06738ebf28b068e1bd63f246982.tar.xz | |
soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC
Switch to using Jasper Lake SoC code from soc/intel/jasperlake and stop
referring from soc/intel/tigerlake.
Addtionally mainboard changes are done to support build.
BUG=b:150217037
TEST=Build and boot waddledoo. Build jasperlake_rvp and volteer board.
Change-Id: I39f117bd66cb610a305bcdb8ea65332fd0ff4814
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/mainboard/google/dedede/romstage.c')
| -rw-r--r-- | src/mainboard/google/dedede/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/dedede/romstage.c b/src/mainboard/google/dedede/romstage.c index 9c220d4538..f95e7aacc3 100644 --- a/src/mainboard/google/dedede/romstage.c +++ b/src/mainboard/google/dedede/romstage.c @@ -6,7 +6,7 @@ */ #include <baseboard/variants.h> -#include <soc/meminit_jsl.h> +#include <soc/meminit.h> #include <soc/romstage.h> void mainboard_memory_init_params(FSPM_UPD *memupd) |