diff options
| author | Aamir Bohra <aamir.bohra@intel.com> | 2020-02-26 00:40:42 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-02-27 19:29:35 +0000 |
| commit | 1ad159094bb3445e0def0f94b38cbcc57d6e9db0 (patch) | |
| tree | d00c64426fa70bbadcd4205939f307373064b67e /src/mainboard/google/dedede/variants/baseboard/devicetree.cb | |
| parent | 6f1bebe9842ae61db7c15af1bbc59a9be367877d (diff) | |
| download | coreboot-1ad159094bb3445e0def0f94b38cbcc57d6e9db0.tar.xz | |
mb/google/dedede: configure ESPI IO decode range for chrome EC
Configure below ESPI IO decode ranges:
1. 0x200-020F: EC host command range.
2. 0x800-0x8FF: EC host command args and params.
3. 0x900-0x9ff: EC memory map range.
Change-Id: I1e450d6e45242180de715746b9852634de2669c6
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/dedede/variants/baseboard/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 2529e53feb..d5f58bae3e 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -20,6 +20,12 @@ chip soc/intel/tigerlake register "pmc_gpe0_dw1" = "GPP_C" register "pmc_gpe0_dw2" = "GPP_D" + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + # USB Port Configuration register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C0 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C1 |