diff options
author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2020-02-06 17:58:07 -0700 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-17 15:35:53 +0000 |
commit | 2a3cef29d81ab9200b8226be41a09f975c9ed485 (patch) | |
tree | e7f1dbd350864861a33c39264b56f7c139c8e899 /src/mainboard/google/dedede/variants/baseboard/devicetree.cb | |
parent | 47607bdc83558f63b917b4de2e35741fe5366469 (diff) | |
download | coreboot-2a3cef29d81ab9200b8226be41a09f975c9ed485.tar.xz |
mb/google/dedede: Enable AP <-> H1 Communication
Turn on the H1 device in the devicetree. Configure the concerned GPIOs
and enable the required config items.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I37972635454cd0d35608623e7be4110012ace658
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38772
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/dedede/variants/baseboard/devicetree.cb')
-rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 29 |
1 files changed, 26 insertions, 3 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 2a0b760728..e98b686608 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -29,13 +29,13 @@ chip soc/intel/tigerlake }" register "SerialIoGSpiMode" = "{ - [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI0] = PchSerialIoPci, [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, }" register "SerialIoGSpiCsMode" = "{ - [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI0] = 1, [PchSerialIoIndexGSPI1] = 0, [PchSerialIoIndexGSPI2] = 0, }" @@ -52,6 +52,22 @@ chip soc/intel/tigerlake [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + }" + device domain 0 on device pci 00.0 off end # Host Bridge device pci 02.0 off end # Integrated Graphics Device @@ -87,7 +103,14 @@ chip soc/intel/tigerlake device pci 1c.7 off end # PCI Express Root Port 8 device pci 1e.0 off end # UART 0 device pci 1e.1 off end # UART 1 - device pci 1e.2 off end # GSPI 0 + device pci 1e.2 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B4_IRQ)" + device spi 0 on end + end + end # GSPI 0 device pci 1e.3 off end # GSPI 1 device pci 1f.0 on chip ec/google/chromeec |