diff options
| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2020-02-07 17:37:17 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-17 15:36:07 +0000 |
| commit | 95ea799019fdb7c0baee70bd07196910dbc0cd95 (patch) | |
| tree | b8ee169779a55b4e2c55f8e24026c5c74903a80e /src/mainboard/google/dedede/variants/baseboard/devicetree.cb | |
| parent | 2a3cef29d81ab9200b8226be41a09f975c9ed485 (diff) | |
| download | coreboot-95ea799019fdb7c0baee70bd07196910dbc0cd95.tar.xz | |
mb/google/dedede: Add console UART configuration
Enable UART Port 2 as console UART and configure the concerned GPIOs.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I30a64a3c96226ce3244d55919b6d65fbf0a096e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38776
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/dedede/variants/baseboard/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index e98b686608..4b2a3c5b13 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -49,7 +49,7 @@ chip soc/intel/tigerlake register "SerialIoUartMode" = "{ [PchSerialIoIndexUART0] = PchSerialIoDisabled, [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }" # Intel Common SoC Config @@ -91,7 +91,7 @@ chip soc/intel/tigerlake device pci 17.0 off end # SATA device pci 19.0 off end # I2C 4 device pci 19.1 off end # I2C 5 - device pci 19.2 off end # UART 2 + device pci 19.2 on end # UART 2 device pci 1a.0 off end # eMMC device pci 1c.0 off end # PCI Express Root Port 1 device pci 1c.1 off end # PCI Express Root Port 2 |