diff options
| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2020-06-06 16:36:05 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-06-08 03:43:35 +0000 |
| commit | aaebfa800c002b778ccac8d15d4054778e85b5f0 (patch) | |
| tree | 4b96abb0586c6ee1ca177ccfba7c962811619d30 /src/mainboard/google/dedede/variants/baseboard/devicetree.cb | |
| parent | 4dbe84e432427e41eca31eb07681372799b9e75e (diff) | |
| download | coreboot-aaebfa800c002b778ccac8d15d4054778e85b5f0.tar.xz | |
mb/google/dedede: source soc_common_config from variants overridetree
All variants are overriding soc_common_config, so source it from
overridetree and remove entry from baseboard devicetree.
Only keeping chipset lockdown config in baseboard which will be
common across all the variants.
BUG=None
BRANCH=None
TEST=Checked code compilation and lockdown config is applied to all variants
Change-Id: I23714b721a6bb0bac785f046586790a98dc5b646
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Diffstat (limited to 'src/mainboard/google/dedede/variants/baseboard/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 42 |
1 files changed, 5 insertions, 37 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index b5112593bc..0b69f7d5cf 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -141,43 +141,11 @@ chip soc/intel/jasperlake # Enable Speed Shift Technology support register "speed_shift_enable" = "1" - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| I2C0 | Trackpad | - #| I2C1 | Digitizer | - #| I2C2 | Touchscreen | - #| I2C3 | Camera | - #| I2C4 | Audio | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[4] = { - .speed = I2C_SPEED_FAST, - }, - }" + # chipset_lockdown configuration + # Use below format to override value in overridetree.cb if required + # format: + # register "common_soc_config.<variable_name>" = "value" + register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT device domain 0 on device pci 00.0 on end # Host Bridge |