diff options
| author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2020-06-18 14:10:10 +0530 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-06-24 16:03:26 +0000 |
| commit | d92d0e24ae47a2e0fcb0bd580056fe9aa8369d60 (patch) | |
| tree | 2ded858c50a635aeee082597d198f9dbde0ebebf /src/mainboard/google/dedede/variants/baseboard/devicetree.cb | |
| parent | 8c28e51a16e13871941048a8312d1830379f725e (diff) | |
| download | coreboot-d92d0e24ae47a2e0fcb0bd580056fe9aa8369d60.tar.xz | |
jasperlake: enable DPTF functionality for dedede
Enable DPTF functionality on jasperlake based dedede platform
BRANCH=None
BUG=None
TEST=Built for dedede system
Change-Id: I17b6e4e96abee6181b0d1f94c356a32aa82c19b9
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41668
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/dedede/variants/baseboard/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 7fdf438f29..f95d123745 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -144,6 +144,17 @@ chip soc/intel/jasperlake # Enable Speed Shift Technology support register "speed_shift_enable" = "1" + # Enable DPTF + register "dptf_enable" = "1" + + register "power_limits_config" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + }" + + # Enable processor thermal control + register "Device4Enable" = "1" + # chipset_lockdown configuration # Use below format to override value in overridetree.cb if required # format: @@ -153,7 +164,7 @@ chip soc/intel/jasperlake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA Thermal device + device pci 04.0 on end # SA Thermal device device pci 05.0 off end # IPU device pci 09.0 off end # Intel Trace Hub device pci 12.6 off end # GSPI 2 |