diff options
| author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2020-06-18 14:10:10 +0530 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-06-24 16:03:26 +0000 |
| commit | d92d0e24ae47a2e0fcb0bd580056fe9aa8369d60 (patch) | |
| tree | 2ded858c50a635aeee082597d198f9dbde0ebebf /src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/dptf.asl | |
| parent | 8c28e51a16e13871941048a8312d1830379f725e (diff) | |
| download | coreboot-d92d0e24ae47a2e0fcb0bd580056fe9aa8369d60.tar.xz | |
jasperlake: enable DPTF functionality for dedede
Enable DPTF functionality on jasperlake based dedede platform
BRANCH=None
BUG=None
TEST=Built for dedede system
Change-Id: I17b6e4e96abee6181b0d1f94c356a32aa82c19b9
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41668
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/dptf.asl')
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/dptf.asl | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/dptf.asl new file mode 100644 index 0000000000..f6b16b456f --- /dev/null +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Below values might change after Thermal Tuning. */ +#define DPTF_CPU_PASSIVE 90 +#define DPTF_CPU_CRITICAL 99 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Memory" +#define DPTF_TSR0_PASSIVE 80 +#define DPTF_TSR0_CRITICAL 90 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Ambient" +#define DPTF_TSR1_PASSIVE 55 +#define DPTF_TSR1_CRITICAL 80 + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 100, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 150, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 6000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 6000, /* PowerLimitMinimum */ + 20000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) |