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authorAamir Bohra <aamir.bohra@intel.com>2020-02-26 20:22:14 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-02-27 17:10:24 +0000
commit6f1bebe9842ae61db7c15af1bbc59a9be367877d (patch)
treee086286059d0d53908f52aa2193ade9863bb49cd /src/mainboard/google/dedede/variants
parentb7fb24677c4adff1d7648de260c3ee9e7f5b45ee (diff)
downloadcoreboot-6f1bebe9842ae61db7c15af1bbc59a9be367877d.tar.xz
mb/google/dedede: Enable display support
1. Enable Internal Gfx device. 2. Configure DDI0 for EDP. 3. Configure HPD and DDC suppport for DDI1/DDI2. 4. Configure HPD GPIOs. TEST=Verify display on EDP panel in OS Change-Id: Ia53428af549ba01ab539f9474a6e5e79b72dff5c Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39132 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/dedede/variants')
-rw-r--r--src/mainboard/google/dedede/variants/baseboard/devicetree.cb13
-rw-r--r--src/mainboard/google/dedede/variants/baseboard/gpio.c4
2 files changed, 16 insertions, 1 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index 37bb8f23c2..2529e53feb 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -73,6 +73,17 @@ chip soc/intel/tigerlake
# Enable EMMC HS400 mode
register "ScsEmmcHs400Enabled" = "1"
+ # Display related UPDs
+ # Select eDP for port A
+ register "DdiPortAConfig" = "1"
+
+ # Enable HPD for DDI ports B/C
+ register "DdiPortBHpd" = "1"
+ register "DdiPortCHpd" = "1"
+ # Enable DDC for DDI ports B/C
+ register "DdiPortBDdc" = "1"
+ register "DdiPortCDdc" = "1"
+
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
@@ -111,7 +122,7 @@ chip soc/intel/tigerlake
device domain 0 on
device pci 00.0 on end # Host Bridge
- device pci 02.0 off end # Integrated Graphics Device
+ device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 off end # SA Thermal device
device pci 05.0 off end # IPU
device pci 09.0 off end # Intel Trace Hub
diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c
index fa975e796b..b8ceae2f8c 100644
--- a/src/mainboard/google/dedede/variants/baseboard/gpio.c
+++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c
@@ -27,6 +27,8 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_A13, NONE),
/* A14 : USB_OC3_N */
PAD_NC(GPP_A14, NONE),
+ /* A16 : EC_AP_USB_C0_HPD */
+ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
/* A18 : USB_OC0_N */
PAD_NC(GPP_A18, NONE),
@@ -40,6 +42,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
/* B18 : H1_SLAVE_SPI_MOSI_R */
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+ /* B23 : EC_AP_USB_C1_HDMI_HPD */
+ PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1),
/* C16 : AP_I2C_TRACKPAD_SDA_3V3 */
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),