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authorKarthikeyan Ramasubramanian <kramasub@google.com>2020-02-28 17:00:14 -0700
committerMartin Roth <martinroth@google.com>2020-03-14 23:31:05 +0000
commitf354c8c6258aa30c545c78c454c2e174b19abeae (patch)
tree1e34566350c5cd51f1e8f61fd8981fef903c224e /src/mainboard/google/dedede/variants
parent136e0cbbc139356e39d7f0457dd05cac1ee5183f (diff)
downloadcoreboot-f354c8c6258aa30c545c78c454c2e174b19abeae.tar.xz
mb/google/dedede: Configure WLAN
Turn on CNVi device. Turn on PCIe Root port that hosts WLAN device. Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN - both CNVi and M.2. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I9bb8e57cdb688bc544929c94af380b9ef1d936a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/dedede/variants')
-rw-r--r--src/mainboard/google/dedede/variants/baseboard/devicetree.cb16
-rw-r--r--src/mainboard/google/dedede/variants/baseboard/gpio.c31
-rw-r--r--src/mainboard/google/dedede/variants/waddledoo/overridetree.cb7
3 files changed, 35 insertions, 19 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index 5a635b32c3..9a8ad66cdd 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -84,12 +84,14 @@ chip soc/intel/tigerlake
register "PcieRpEnable[4]" = "0"
register "PcieRpEnable[5]" = "0"
register "PcieRpEnable[6]" = "0"
- register "PcieRpEnable[7]" = "0"
+ # PCIe Root Port 8 (index 7) hosts M.2 E-key WLAN.
+ register "PcieRpEnable[7]" = "1"
register "PcieClkSrcUsage[0]" = "0xff"
register "PcieClkSrcUsage[1]" = "0xff"
register "PcieClkSrcUsage[2]" = "0xff"
- register "PcieClkSrcUsage[3]" = "0xff"
+ # PCIe Clock Source 4 (index 3) is used by WLAN on PCIe Root Port 8 (index 7)
+ register "PcieClkSrcUsage[3]" = "7"
register "PcieClkSrcUsage[4]" = "0xff"
register "PcieClkSrcUsage[5]" = "0xff"
@@ -222,7 +224,10 @@ chip soc/intel/tigerlake
end # USB xHCI
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 off end # PMC SRAM
- device pci 14.3 off end # CNVi wifi
+ chip drivers/intel/wifi
+ register "wake" = "GPE0_PME_B0"
+ device pci 14.3 on end # CNVi wifi
+ end
device pci 14.5 off end # SDCard
device pci 15.0 on end # I2C 0
device pci 15.1 on end # I2C 1
@@ -240,11 +245,12 @@ chip soc/intel/tigerlake
device pci 1c.0 off end # PCI Express Root Port 1
device pci 1c.1 off end # PCI Express Root Port 2
device pci 1c.2 off end # PCI Express Root Port 3
- device pci 1c.3 off end # PCI Express Root Port 4 - WLAN
+ device pci 1c.3 off end # PCI Express Root Port 4
device pci 1c.4 off end # PCI Express Root Port 5
device pci 1c.5 off end # PCI Express Root Port 6
device pci 1c.6 off end # PCI Express Root Port 7
- device pci 1c.7 off end # PCI Express Root Port 8
+ # External PCIe port 4 is mapped to PCIe Root port 8
+ device pci 1c.7 on end # PCI Express Root Port 8 - WLAN
device pci 1e.0 off end # UART 0
device pci 1e.1 off end # UART 1
device pci 1e.2 on
diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c
index 20c7be9123..13419b8b66 100644
--- a/src/mainboard/google/dedede/variants/baseboard/gpio.c
+++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c
@@ -64,8 +64,8 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_B6, NONE),
/* B7 : PCIE_CLKREQ2_N */
PAD_NC(GPP_B7, NONE),
- /* B8 : PCIE_CLKREQ3_N */
- PAD_NC(GPP_B8, NONE),
+ /* B8 : WLAN_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
/* B9 : PCIE_CLKREQ4_N */
PAD_NC(GPP_B9, NONE),
/* B10 : PCIE_CLKREQ5_N */
@@ -149,11 +149,11 @@ static const struct pad_config gpio_table[] = {
/* D0 : WWAN_HOST_WAKE */
PAD_NC(GPP_D0, NONE),
/* D1 : WLAN_PERST_L */
- PAD_NC(GPP_D1, NONE),
+ PAD_CFG_GPO(GPP_D1, 1, DEEP),
/* D2 : WLAN_INT_L */
PAD_NC(GPP_D2, NONE),
/* D3 : WLAN_PCIE_WAKE_ODL */
- PAD_NC(GPP_D3, NONE),
+ PAD_CFG_GPI_SCI_LOW(GPP_D3, NONE, DEEP, EDGE_SINGLE),
/* D4 : TOUCH_INT_ODL */
PAD_NC(GPP_D4, NONE),
/* D5 : TOUCH_RESET_L */
@@ -185,11 +185,11 @@ static const struct pad_config gpio_table[] = {
/* D18 : I2S_MCLK */
PAD_NC(GPP_D18, NONE),
/* D19 : WWAN_WLAN_COEX1 */
- PAD_NC(GPP_D19, NONE),
+ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
/* D20 : WWAN_WLAN_COEX2 */
- PAD_NC(GPP_D20, NONE),
+ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
/* D21 : WWAN_WLAN_COEX3 */
- PAD_NC(GPP_D21, NONE),
+ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
/* D22 : AP_I2C_SUB_SDA*/
PAD_NC(GPP_D22, NONE),
/* D23 : AP_I2C_SUB_SCL */
@@ -236,17 +236,17 @@ static const struct pad_config gpio_table[] = {
/* E19 : GPP_E19/IMGCLKOUT_5/PCIE_LNK_DOWN */
PAD_NC(GPP_E19, NONE),
/* E20 : CNV_BRI_DT_R */
- PAD_NC(GPP_E20, NONE),
+ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
/* E21 : CNV_BRI_RSP */
- PAD_NC(GPP_E21, NONE),
+ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
/* E22 : CNV_RGI_DT_R */
- PAD_NC(GPP_E22, NONE),
+ PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1),
/* E23 : CNV_RGI_RSP */
- PAD_NC(GPP_E23, NONE),
+ PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
/* F4 : CNV_RF_RST_L */
- PAD_NC(GPP_F4, NONE),
+ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
/* F7 : EMMC_CMD */
PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1),
/* F8 : EMMC_DATA0 */
@@ -294,7 +294,7 @@ static const struct pad_config gpio_table[] = {
/* H1 : EN_PP3300_SD_U */
PAD_NC(GPP_H1, NONE),
/* H2 : CNV_CLKREQ0 */
- PAD_NC(GPP_H2, NONE),
+ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3),
/* H3 : GPP_H03/SX_EXIT_HOLDOFF_N */
PAD_NC(GPP_H3, NONE),
/* H4 : AP_I2C_TS_SDA */
@@ -326,7 +326,7 @@ static const struct pad_config gpio_table[] = {
/* H17 : WWAN_RST_L */
PAD_NC(GPP_H17, NONE),
/* H18 : WLAN_DISABLE_L */
- PAD_NC(GPP_H18, NONE),
+ PAD_CFG_GPO(GPP_H18, 1, DEEP),
/* H19 : BT_DISABLE_L */
PAD_CFG_GPO(GPP_H19, 1, DEEP),
@@ -410,6 +410,9 @@ static const struct pad_config early_gpio_table[] = {
/* C5 : RAM_STRAP_3 */
PAD_CFG_GPI(GPP_C5, NONE, DEEP),
+ /* D1 : WLAN_PERST_L */
+ PAD_CFG_GPO(GPP_D1, 1, DEEP),
+
/* H19 : BT_DISABLE_L */
PAD_CFG_GPO(GPP_H19, 0, DEEP),
};
diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb
index 061a0f865f..9860e3de46 100644
--- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb
@@ -49,5 +49,12 @@ chip soc/intel/tigerlake
device i2c 15 on end
end
end #I2C 0
+
+ device pci 1c.7 on
+ chip drivers/intel/wifi
+ register "wake" = "GPE0_DW2_03"
+ device pci 00.0 on end
+ end
+ end # PCI Express Root Port 8 - WLAN
end
end