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| author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2020-06-30 15:15:28 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-07-01 19:04:30 +0000 |
| commit | 15311d246f42cefc29b0d8d9bb098704e8ea6308 (patch) | |
| tree | 8cbc3aea08451533fd14e19efc5ad0c80f0ba29a /src/mainboard/google/dedede | |
| parent | ca18073861bcd8eb9f7b10d3919b3fdc4676ce14 (diff) | |
| download | coreboot-15311d246f42cefc29b0d8d9bb098704e8ea6308.tar.xz | |
mb/google/dedede: set tcc_offset value to 10
Set tcc_offset value to 10 in devicetree for Thermal Control
Circuit (TCC) activation feature.
BUG=None
BRANCH=None
TEST=Built for dedede platform and verified the MSR value
Change-Id: I53d1bd413c64643cf8bdaef266bde25a2f3a97ee
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42906
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/dedede')
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index f95d123745..32f6690339 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -155,6 +155,8 @@ chip soc/intel/jasperlake # Enable processor thermal control register "Device4Enable" = "1" + register "tcc_offset" = "10" # TCC of 90C + # chipset_lockdown configuration # Use below format to override value in overridetree.cb if required # format: |