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| author | Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> | 2021-03-17 17:44:51 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-25 07:49:26 +0000 |
| commit | 57c013eb11b1c918079eb0e87bf4c23db85bc13c (patch) | |
| tree | 562fdca53381a305562bb12932da31cbc852440f /src/mainboard/google/dedede | |
| parent | 4119391a8e02578b514a16735aa845366d05c774 (diff) | |
| download | coreboot-57c013eb11b1c918079eb0e87bf4c23db85bc13c.tar.xz | |
mb/google/dedede/var/cret: Configure USB port settings
Follow schematic to modify USB port settings.
USB2 [0]: USB Type C Port 0
USB2 [1]: None
USB2 [2]: USB Type A Port 0
USB2 [3]: LTE
USB2 [4]: None
USB2 [5]: Camera UFC
USB2 [6]: Camera WFC
USB2 [7]: Integrated Bluetooth
USB3 [0]: USB Type C Port 0 (M/B side)
USB3 [1]: None
USB3 [2]: USB Type A Port 0 (M/B side)
USB3 [3]: LTE
BUG=b:182973703
BRANCH=dedede
TEST=Build the coreboot image.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I80447d6ac3422f858a9022f550b4f42353819405
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/mainboard/google/dedede')
| -rw-r--r-- | src/mainboard/google/dedede/variants/cret/overridetree.cb | 40 |
1 files changed, 39 insertions, 1 deletions
diff --git a/src/mainboard/google/dedede/variants/cret/overridetree.cb b/src/mainboard/google/dedede/variants/cret/overridetree.cb index 806349e976..0521f20596 100644 --- a/src/mainboard/google/dedede/variants/cret/overridetree.cb +++ b/src/mainboard/google/dedede/variants/cret/overridetree.cb @@ -1,6 +1,13 @@ chip soc/intel/jasperlake # USB Port Configuration + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # None + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # LTE + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # None + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera (UFC) + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera (WFC) + register "usb3_ports[1]" = "USB3_PORT_EMPTY" # None + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # LTE # Intel Common SoC Config #+-------------------+---------------------------+ @@ -38,7 +45,38 @@ chip soc/intel/jasperlake }, }" device domain 0 on - device pci 14.0 on end + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + device usb 2.1 off end + end + chip drivers/usb/acpi + register "desc" = ""LTE"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""Camera (UFC)"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""Camera (WFC)"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + chip drivers/usb/acpi + device usb 3.1 off end + end + chip drivers/usb/acpi + register "desc" = ""LTE"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.3 on end + end + end + end + end # USB xHCI device pci 15.0 on end device pci 15.2 on end device pci 1c.7 on end |