diff options
| author | Ian Feng <ian_feng@compal.corp-partner.google.com> | 2020-04-17 16:45:08 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-04-20 06:26:17 +0000 |
| commit | c423293d200cfa8ff7162a07fcd365a58347ab7e (patch) | |
| tree | 6f819c7700e4819f5be35ae6f46ebaa52551645a /src/mainboard/google/dedede | |
| parent | da38715ec3cef00ffa893a2adbee30674bf5f9a4 (diff) | |
| download | coreboot-c423293d200cfa8ff7162a07fcd365a58347ab7e.tar.xz | |
mb/google/dedede: Disable dynamic clock gating for cr50's GPIO
Disable dynamic clock gating for the community cr50's IRQ lives on.
That IRQ is pulsed very quickly, and with clock gating enabled pulses
tend to be missed. This is expecially true on the default 0.0.22
firmware that cr50 comes with out of the factory.
BUG=b:154178408 b:154293730
BRANCH=None
TEST=build waddledoo successful and Linux has no TPM IRQ timeout error.
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I2b1b3ee59ebf6adce0653e7550b457e02d3c87df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/mainboard/google/dedede')
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index f030b20cec..cfe221f994 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -118,6 +118,14 @@ chip soc/intel/jasperlake # Select eDP for port A register "DdiPortAConfig" = "1" + # Disable PM to allow for shorter irq pulses + register "gpio_override_pm" = "1" + register "gpio_pm[0]" = "0" + register "gpio_pm[1]" = "0" + register "gpio_pm[2]" = "0" + register "gpio_pm[3]" = "0" + register "gpio_pm[4]" = "0" + # Enable HPD for DDI ports B/C register "DdiPortBHpd" = "1" register "DdiPortCHpd" = "1" |