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authorKarthikeyan Ramasubramanian <kramasub@google.com>2020-02-12 12:07:51 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-02-24 12:31:12 +0000
commitbe6583ae5c98ccae7f58bda9389fbf7458787612 (patch)
tree3b6dc4289986bee90218200d90fb95cbb02a1099 /src/mainboard/google/dedede
parent7225ed60351c48eee93f1e163e4d42480bc72185 (diff)
downloadcoreboot-be6583ae5c98ccae7f58bda9389fbf7458787612.tar.xz
mb/google/dedede: Add EMMC configuration
Turn on EMMC device and enable the HS400 mode. Configure the GPIOs associated with EMMC. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ic27c68f4622eec5b2930dc38186b82d895d3f67c Reviewed-on: https://review.coreboot.org/c/coreboot/+/38856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Diffstat (limited to 'src/mainboard/google/dedede')
-rw-r--r--src/mainboard/google/dedede/variants/baseboard/devicetree.cb5
-rw-r--r--src/mainboard/google/dedede/variants/baseboard/gpio.c25
2 files changed, 29 insertions, 1 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index 9dfd6b7536..c17620b3e7 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -69,6 +69,9 @@ chip soc/intel/tigerlake
[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
}"
+ # Enable EMMC HS400 mode
+ register "ScsEmmcHs400Enabled" = "1"
+
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
@@ -129,7 +132,7 @@ chip soc/intel/tigerlake
device pci 19.0 on end # I2C 4
device pci 19.1 off end # I2C 5
device pci 19.2 on end # UART 2
- device pci 1a.0 off end # eMMC
+ device pci 1a.0 on end # eMMC
device pci 1c.0 off end # PCI Express Root Port 1
device pci 1c.1 off end # PCI Express Root Port 2
device pci 1c.2 off end # PCI Express Root Port 3
diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c
index 71ddadbf95..fa975e796b 100644
--- a/src/mainboard/google/dedede/variants/baseboard/gpio.c
+++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c
@@ -58,6 +58,31 @@ static const struct pad_config gpio_table[] = {
/* C23 : UART2_CTS_N */
PAD_NC(GPP_C23, DN_20K),
+ /* F7 : EMMC_CMD */
+ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1),
+ /* F8 : EMMC_DATA0 */
+ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
+ /* F9 : EMMC_DATA1 */
+ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
+ /* F10 : EMMC_DATA2 */
+ PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1),
+ /* F11 : EMMC_DATA3 */
+ PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
+ /* F12 : EMMC_DATA4 */
+ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
+ /* F13 : EMMC_DATA5 */
+ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
+ /* F14 : EMMC_DATA6 */
+ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
+ /* F15 : EMMC_DATA7 */
+ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
+ /* F16 : EMMC_RCLK */
+ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
+ /* F17 : EMMC_CLK */
+ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
+ /* F18 : EMMC_RESET_N */
+ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
+
/* H4 : AP_I2C_TS_SDA */
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
/* H5 : AP_I2C_TS_SCL */