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| author | Aamir Bohra <aamir.bohra@intel.com> | 2018-07-11 12:07:51 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-27 09:00:49 +0000 |
| commit | 3a14338625d6ae7c6c4e8ee0b1e9be285593b3a6 (patch) | |
| tree | 75e78040495541302dbc483bd87a36d51981b8d3 /src/mainboard/google/dragonegg/Kconfig | |
| parent | 13415333fedada138515a986afab799ca05a785f (diff) | |
| download | coreboot-3a14338625d6ae7c6c4e8ee0b1e9be285593b3a6.tar.xz | |
mb/google/dragonegg: Add initial mainboard code support
This patch includes support for both ICL ES0 and ES1 samples.
Detailed document is here: Documentation/soc/intel/icelake/iceLake_coreboot_development.md
TEST=Able to build and boot dragonegg.
Change-Id: I2cc269cb0050bf5b031f48cfe114485c55ab8fa9
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/29749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/google/dragonegg/Kconfig')
| -rw-r--r-- | src/mainboard/google/dragonegg/Kconfig | 83 |
1 files changed, 83 insertions, 0 deletions
diff --git a/src/mainboard/google/dragonegg/Kconfig b/src/mainboard/google/dragonegg/Kconfig new file mode 100644 index 0000000000..18382d5307 --- /dev/null +++ b/src/mainboard/google/dragonegg/Kconfig @@ -0,0 +1,83 @@ +config BOARD_GOOGLE_BASEBOARD_DRAGONEGG + def_bool n + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_SPI_ACPI + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_LPC + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_CHROMEOS + select SOC_INTEL_ICELAKE + +if BOARD_GOOGLE_BASEBOARD_DRAGONEGG + +config CHROMEOS + bool + default y + select GBB_FLAG_FORCE_MANUAL_RECOVERY + +config DEVICETREE + string + default "variants/baseboard/devicetree.cb" + +config DIMM_SPD_SIZE + int + default 512 + +# Select this option to enable use of cr50 SPI TPM on dragon egg. +config DRAGONEGG_USE_SPI_TPM + bool + default y + select MAINBOARD_HAS_SPI_TPM_CR50 + select MAINBOARD_HAS_TPM2 + +config DRIVER_TPM_SPI_BUS + depends on DRAGONEGG_USE_SPI_TPM + default 0x1 + +config GBB_HWID + string + depends on CHROMEOS + default "DRAGONEGG TEST 1394" + +config MAINBOARD_DIR + string + default "google/dragonegg" + +config MAINBOARD_PART_NUMBER + string + default "Dragonegg" + +config MAINBOARD_VENDOR + string + default "Google" + +config MAINBOARD_FAMILY + string + default "Google_Dragonegg" + +config MAX_CPUS + int + default 8 + +config TPM_TIS_ACPI_INTERRUPT + int + default 48 # GPE0_DW1_16 (GPP_D16) + +config VARIANT_DIR + string + default "dragonegg" if BOARD_GOOGLE_DRAGONEGG + +config UART_FOR_CONSOLE + int + default 0 + +config VBOOT + select VBOOT_LID_SWITCH + select EC_GOOGLE_CHROMEEC_SWITCHES + select HAS_RECOVERY_MRC_CACHE + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN + +endif # BOARD_GOOGLE_BASEBOARD_DRAGONEGG |