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author | Aamir Bohra <aamir.bohra@intel.com> | 2018-07-11 12:07:51 +0530 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-27 09:00:49 +0000 |
commit | 3a14338625d6ae7c6c4e8ee0b1e9be285593b3a6 (patch) | |
tree | 75e78040495541302dbc483bd87a36d51981b8d3 /src/mainboard/google/dragonegg/dsdt.asl | |
parent | 13415333fedada138515a986afab799ca05a785f (diff) | |
download | coreboot-3a14338625d6ae7c6c4e8ee0b1e9be285593b3a6.tar.xz |
mb/google/dragonegg: Add initial mainboard code support
This patch includes support for both ICL ES0 and ES1 samples.
Detailed document is here: Documentation/soc/intel/icelake/iceLake_coreboot_development.md
TEST=Able to build and boot dragonegg.
Change-Id: I2cc269cb0050bf5b031f48cfe114485c55ab8fa9
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/29749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/google/dragonegg/dsdt.asl')
-rw-r--r-- | src/mainboard/google/dragonegg/dsdt.asl | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/src/mainboard/google/dragonegg/dsdt.asl b/src/mainboard/google/dragonegg/dsdt.asl new file mode 100644 index 0000000000..0d08cf7647 --- /dev/null +++ b/src/mainboard/google/dragonegg/dsdt.asl @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include "variant/ec.h" +#include "variant/gpio.h" + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/icelake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/icelake/acpi/globalnvs.asl> + + // CPU + #include <soc/intel/icelake/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/icelake/acpi/northbridge.asl> + #include <soc/intel/icelake/acpi/southbridge.asl> + } + } + +#if IS_ENABLED(CONFIG_CHROMEOS) + // Chrome OS specific + #include <vendorcode/google/chromeos/acpi/chromeos.asl> +#endif + + // Chipset specific sleep states + #include <soc/intel/icelake/acpi/sleepstates.asl> + + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } +} |