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| author | Subrata Banik <subrata.banik@intel.com> | 2018-11-20 14:32:58 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-06-09 02:47:55 +0000 |
| commit | 4b8f5a351799dd22d8924b8bea4a3e666893f965 (patch) | |
| tree | 891b155595418bf32f5a76c8cf2be0ee4440bbb7 /src/mainboard/google/dragonegg/variants | |
| parent | 2ee8fe0094da413fe57796131d7c3b9f927f68a1 (diff) | |
| download | coreboot-4b8f5a351799dd22d8924b8bea4a3e666893f965.tar.xz | |
mb/google/dragonegg: Pass FSP-M UPD as per dragonegg requirement
TEST=Able to boot dragonegg board with LPDDR4 memory.
Change-Id: Idbe0aa79879f2b1a754dd1f6718ad4ba1173e760
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31956
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/dragonegg/variants')
| -rw-r--r-- | src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb index f820924280..b3b93f55ca 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb @@ -102,8 +102,8 @@ chip soc/intel/icelake [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, - [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoSkipInit, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, }" register "SerialIoGSpiMode" = "{ |