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authorEric Lai <ericr_lai@compal.corp-partner.google.com>2019-09-06 11:57:23 +0800
committerPatrick Georgi <pgeorgi@google.com>2019-09-09 13:29:08 +0000
commitd6c2d1df2cbe190743fdd97d4fdabd33518db6a8 (patch)
tree4cb6a8155e3eb94c4c628b717fc3bb7ed9cff487 /src/mainboard/google/drallion/variants
parent59613ee27016613fcd36b15e5d98d5ff95b3068f (diff)
downloadcoreboot-d6c2d1df2cbe190743fdd97d4fdabd33518db6a8.tar.xz
mb/google/drallion: modify USB setting
Based on HW schematic to modify USB setting. Drallion has two type C on left and two type A on right. BUG=b:138082886 BRANCH=N/A TEST=N/A Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I925de209635d92ef61ccb9114efebb4b10f30e87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
Diffstat (limited to 'src/mainboard/google/drallion/variants')
-rw-r--r--src/mainboard/google/drallion/variants/drallion/devicetree.cb67
1 files changed, 31 insertions, 36 deletions
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index 561217a76a..e96f9d739d 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -131,29 +131,22 @@ chip soc/intel/cannonlake
}"
# Intel Common SoC Config
- register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port
- register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Left Type-A Port
- register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Right Type-A Port
- register "usb2_ports[3]" = "USB2_PORT_EMPTY"
- register "usb2_ports[4]" = "USB2_PORT_EMPTY"
+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port 1
+ register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port 2
+ register "usb2_ports[2]" = "USB2_PORT_LONG(OC0)" # Right Type-A Port 1
+ register "usb2_ports[3]" = "USB2_PORT_LONG(OC1)" # Right Type-A Port 2
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # WWAN
register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera
- register "usb2_ports[6]" = "{
- .enable = 1, \
- .ocpin = OC_SKIP, \
- .tx_bias = USB2_BIAS_0MV, \
- .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \
- .pre_emp_bias = USB2_BIAS_28P15MV, \
- .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
- }" # WWAN
- register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH
- register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+ register "usb2_ports[6]" = "USB2_PORT_EMPTY"
+ register "usb2_ports[7]" = "USB2_PORT_EMPTY"
+ register "usb2_ports[8]" = "USB2_PORT_EMPTY"
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Left Type-A Port
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN
- register "usb3_ports[4]" = "USB3_PORT_EMPTY"
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port 2
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Right Type-A Port 1
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port 2
+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN
register "usb3_ports[5]" = "USB3_PORT_EMPTY"
# Intel Common SoC Config
@@ -253,8 +246,8 @@ chip soc/intel/cannonlake
device usb 2.0 on end
end
chip drivers/usb/acpi
- register "desc" = ""Left Type-A Port""
- register "type" = "UPC_TYPE_A"
+ register "desc" = ""Left Type-C Port""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(1, 2)"
device usb 2.1 on end
end
@@ -265,24 +258,20 @@ chip soc/intel/cannonlake
device usb 2.2 on end
end
chip drivers/usb/acpi
- register "desc" = ""Camera""
- register "type" = "UPC_TYPE_INTERNAL"
- device usb 2.5 on end
+ register "desc" = ""Right Type-A Port""
+ register "type" = "UPC_TYPE_A"
+ register "group" = "ACPI_PLD_GROUP(2, 2)"
+ device usb 2.3 on end
end
chip drivers/usb/acpi
register "desc" = ""WWAN""
register "type" = "UPC_TYPE_INTERNAL"
- device usb 2.6 on end
- end
- chip drivers/usb/acpi
- register "desc" = ""USH""
- register "type" = "UPC_TYPE_INTERNAL"
- device usb 2.7 on end
+ device usb 2.4 on end
end
chip drivers/usb/acpi
- register "desc" = ""Fingerprint""
+ register "desc" = ""Camera""
register "type" = "UPC_TYPE_INTERNAL"
- device usb 2.8 on end
+ device usb 2.5 on end
end
chip drivers/usb/acpi
register "desc" = ""Bluetooth""
@@ -297,21 +286,27 @@ chip soc/intel/cannonlake
device usb 3.0 on end
end
chip drivers/usb/acpi
- register "desc" = ""Left Type-A Port""
+ register "desc" = ""Right Type-A Port""
register "type" = "UPC_TYPE_USB3_A"
- register "group" = "ACPI_PLD_GROUP(1, 2)"
+ register "group" = "ACPI_PLD_GROUP(2, 1)"
device usb 3.1 on end
end
chip drivers/usb/acpi
register "desc" = ""Right Type-A Port""
register "type" = "UPC_TYPE_USB3_A"
- register "group" = "ACPI_PLD_GROUP(2, 1)"
+ register "group" = "ACPI_PLD_GROUP(2, 2)"
device usb 3.2 on end
end
chip drivers/usb/acpi
+ register "desc" = ""Left Type-C Port""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(1, 2)"
+ device usb 3.3 on end
+ end
+ chip drivers/usb/acpi
register "desc" = ""WWAN""
register "type" = "UPC_TYPE_INTERNAL"
- device usb 3.3 on end
+ device usb 3.4 on end
end
end
end