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authorEric Lai <ericr_lai@compal.corp-partner.google.com>2019-11-01 13:36:37 +0800
committerPatrick Georgi <pgeorgi@google.com>2019-11-04 11:33:44 +0000
commit540757116863f163e59078f6e79f7696f831caa0 (patch)
treeacfe9d1a65d7a80ec1d8bf88d139944113b58ab5 /src/mainboard/google/drallion
parent3d4f51ef695ff2473b963a33cfdfeb4d864d3f4a (diff)
downloadcoreboot-540757116863f163e59078f6e79f7696f831caa0.tar.xz
mb/google/drallion: Update GPIO table
Follow latest GPIO table to change gpio. BUG=b:143728355 BRANCH=N/A TEST=build pass Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Iee61c74a5cab5a62a90c0543f212650c4f2420de Reviewed-on: https://review.coreboot.org/c/coreboot/+/36524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
Diffstat (limited to 'src/mainboard/google/drallion')
-rw-r--r--src/mainboard/google/drallion/variants/drallion/gpio.c9
1 files changed, 4 insertions, 5 deletions
diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c
index 697d3056a6..5657eeaae1 100644
--- a/src/mainboard/google/drallion/variants/drallion/gpio.c
+++ b/src/mainboard/google/drallion/variants/drallion/gpio.c
@@ -39,13 +39,13 @@ static const struct pad_config gpio_table[] = {
/* ESPI_RESET# */
/* SUSACK# */ PAD_CFG_GPO(GPP_A15, 0, DEEP),
/* SD_1P8_SEL */ PAD_CFG_GPI(GPP_A16, NONE, PLTRST), /* 2.7MM_CAM_DET# */
-/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF2),
+/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE),
/* ISH_ACC1_INT# */
/* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
/* ISH_ACC2_INT# */
/* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
/* ISH_GP2 */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
-/* ISH_GP3 */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
+/* ISH_GP3 */ PAD_NC(GPP_A21, NONE),
/* ISH_NB_MODE */
/* ISH_GP4 */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),
/* ISH_LID_CL#_NB */
@@ -63,11 +63,10 @@ static const struct pad_config gpio_table[] = {
/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
/* WLAN_CLKREQ_CPU_N */
/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
- /* WWAN_CLKREQ_CPU_N */
-/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
+/* SRCCLKREQ3# */ PAD_NC(GPP_B8, NONE),
/* SSD_CKLREQ_CPU_N */
/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
-/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE),
/* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, PLTRST), /* 3.3V_CAM_EN# */
/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),