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authorAamir Bohra <aamir.bohra@intel.com>2019-09-27 07:13:46 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-09-28 13:22:07 +0000
commit78d6ce45d4ec5a447ae5837497856c5af236a8d2 (patch)
treedee4badaa968bd250853d64bd595757ff1173c4a /src/mainboard/google/drallion
parent965881b7ce202b8d1e114d23d90a156b9d6e2573 (diff)
downloadcoreboot-78d6ce45d4ec5a447ae5837497856c5af236a8d2.tar.xz
mb/google/drallion: Set UART for console to UART controller 0
Drallion uses UART 0 for console, change the config accordindly. BUG=b:139095062 Change-Id: I0ae2f8459b6225b99b758180413afa22386355d4 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35633 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/drallion')
-rw-r--r--src/mainboard/google/drallion/Kconfig2
-rw-r--r--src/mainboard/google/drallion/variants/drallion/devicetree.cb4
2 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig
index a2ed3d86f9..97d0b51a8d 100644
--- a/src/mainboard/google/drallion/Kconfig
+++ b/src/mainboard/google/drallion/Kconfig
@@ -91,7 +91,7 @@ config MAX_CPUS
config UART_FOR_CONSOLE
int
- default 2
+ default 0
config VARIANT_DIR
string
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index d824a552d0..956e54edf9 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -389,7 +389,7 @@ chip soc/intel/cannonlake
end
end # I2C #4
device pci 19.1 off end # I2C #5
- device pci 19.2 on end # UART #2
+ device pci 19.2 off end # UART #2
device pci 1a.0 off end # eMMC
device pci 1c.0 off end # PCI Express Port 1 (USB)
device pci 1c.1 off end # PCI Express Port 2 (USB)
@@ -408,7 +408,7 @@ chip soc/intel/cannonlake
device pci 1d.4 on
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
end # PCI Express Port 13 (x4)
- device pci 1e.0 off end # UART #0
+ device pci 1e.0 on end # UART #0
device pci 1e.1 off end # UART #1
device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1