summaryrefslogtreecommitdiff
path: root/src/mainboard/google/drallion
diff options
context:
space:
mode:
authorSubrata Banik <subrata.banik@intel.com>2020-01-03 14:50:49 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-01-09 08:25:12 +0000
commitd5be4e4046a1ef89672f57e8c5674f95b66c97ae (patch)
tree82bade23e9466ead8bcaad73f0f0da6bccc061cc /src/mainboard/google/drallion
parenta8280e4cc0bf146ca29030a8d1d50b7276d26c6e (diff)
downloadcoreboot-d5be4e4046a1ef89672f57e8c5674f95b66c97ae.tar.xz
soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi
This patch creates a common instance of northbridge.asl inside intel common code (soc/intel/common/block/acpi/acpi) and changes cnl,icl & tgl soc code to refer northbridge.asl from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify Device(MCHC) presence after booting to OS. Change-Id: Ib9af844bcbbcce3f4b0ac7aada43d43e4171e08b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38155 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/drallion')
-rw-r--r--src/mainboard/google/drallion/dsdt.asl2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl
index 78c6c16a33..ee63d6ee8a 100644
--- a/src/mainboard/google/drallion/dsdt.asl
+++ b/src/mainboard/google/drallion/dsdt.asl
@@ -36,7 +36,7 @@ DefinitionBlock(
Scope (\_SB) {
Device (PCI0)
{
- #include <soc/intel/cannonlake/acpi/northbridge.asl>
+ #include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/cannonlake/acpi/southbridge.asl>
}
/* Per board variant mainboard hooks. */