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authorEric Lai <ericr_lai@compal.corp-partner.google.com>2019-08-28 16:17:56 +0800
committerPatrick Georgi <pgeorgi@google.com>2019-08-30 10:39:04 +0000
commit74de4b85d1e3c6b48fd89b7470d0abef6523f4bb (patch)
tree3bc5730cec998d86bd7c03aeef4a62b03ddff9b9 /src/mainboard/google/drallion
parentb685e921bbea924314a697179943a95dbf280c6b (diff)
downloadcoreboot-74de4b85d1e3c6b48fd89b7470d0abef6523f4bb.tar.xz
mb/google/drallion: change servo board debug to UART 0
Drallion will change debug port UART from 2 to 0. Followed HW schematic to modify it. BUG=b:139095062 BRANCH=N/A TEST=Build without error Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib2bcded8de3c9fb2c0a4ccbd002b1f219bccceb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
Diffstat (limited to 'src/mainboard/google/drallion')
-rw-r--r--src/mainboard/google/drallion/variants/drallion/devicetree.cb4
-rw-r--r--src/mainboard/google/drallion/variants/drallion/gpio.c8
2 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index 575b61014b..54184f0a41 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -355,7 +355,7 @@ chip soc/intel/cannonlake
end
end # I2C #4
device pci 19.1 off end # I2C #5
- device pci 19.2 on end # UART #2
+ device pci 19.2 off end # UART #2
device pci 1a.0 off end # eMMC
device pci 1c.0 off end # PCI Express Port 1 (USB)
device pci 1c.1 off end # PCI Express Port 2 (USB)
@@ -374,7 +374,7 @@ chip soc/intel/cannonlake
device pci 1d.4 on
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
end # PCI Express Port 13 (x4)
- device pci 1e.0 off end # UART #0
+ device pci 1e.0 on end # UART #0
device pci 1e.1 off end # UART #1
device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1
diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c
index ff0240c991..ebe5ee27e1 100644
--- a/src/mainboard/google/drallion/variants/drallion/gpio.c
+++ b/src/mainboard/google/drallion/variants/drallion/gpio.c
@@ -87,8 +87,8 @@ static const struct pad_config gpio_table[] = {
/* SML0ALERT# */ PAD_NC(GPP_C5, DN_20K),
/* SM1CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1_SMBCLK */
/* SM1DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1_SMBDATA */
-/* UART0_RXD */ PAD_NC(GPP_C8, NONE), /* PCH_TBT_PERST# (nostuff) */
-/* UART0_TXD */ PAD_NC(GPP_C9, NONE),
+/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* SERVOTX_UART */
+/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* SERVORX_UART */
/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* TYPEC_CON_SEL1 */
/* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* TYPEC_CON_SEL2 */
/* UART1_RXD */ PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP,
@@ -100,8 +100,8 @@ static const struct pad_config gpio_table[] = {
/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TS_I2C_SCL */
/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SDA_TP */
/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* I2C1_SCK_TP */
-/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */
-/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */
+/* UART2_RXD */ PAD_NC(GPP_C20, NONE),
+/* UART2_TXD */ PAD_NC(GPP_C21, NONE),
/* UART2_RTS# */ PAD_NC(GPP_C22, NONE),
/* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST,
LEVEL, NONE), /* TS_INT# */