diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2016-06-02 17:58:18 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-09-21 13:59:55 +0200 |
| commit | 1ba34323010f075e21ed11d9cf2c97e688441676 (patch) | |
| tree | 12d98710a605745690c58f4adf3635fef5e6bcf0 /src/mainboard/google/enguarde/dsdt.asl | |
| parent | 776498ac7ec537bab2a65101fd9640c1a7679f51 (diff) | |
| download | coreboot-1ba34323010f075e21ed11d9cf2c97e688441676.tar.xz | |
google/enguarde: Upstream Lenovo N21 Chromebook
Migrate google/enguarde (Lenovo N21 Chromebook) from Chromium tree to
upstream, using google/rambi as a reference.
original source:
branch firmware-enguarde-5216.201.B
commit cf1f57b [Enguarde: Adjust rx delay for norm.]
TEST=built and booted Linux on enguarde with full functionality
blobs required for working image:
VGA BIOS (vgabios.bin)
firmware descriptor (ifd.bin)
Intel ME firmware (me.bin)
MRC (mrc.elf)
external reference code (refcode.elf)
Change-Id: I3ccda29d1e095d8b1b36766cda913172f72233a7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/15444
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/google/enguarde/dsdt.asl')
| -rw-r--r-- | src/mainboard/google/enguarde/dsdt.asl | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/src/mainboard/google/enguarde/dsdt.asl b/src/mainboard/google/enguarde/dsdt.asl new file mode 100644 index 0000000000..a20a197244 --- /dev/null +++ b/src/mainboard/google/enguarde/dsdt.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define ENABLE_TPM + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/baytrail/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/baytrail/acpi/globalnvs.asl> + + #include <soc/intel/baytrail/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + //#include <soc/intel/baytrail/acpi/northcluster.asl> + #include <soc/intel/baytrail/acpi/southcluster.asl> + } + + /* Dynamic Platform Thermal Framework */ + #include "acpi/dptf.asl" + } + + #include "acpi/chromeos.asl" + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + /* Chipset specific sleep states */ + #include <soc/intel/baytrail/acpi/sleepstates.asl> + + #include "acpi/mainboard.asl" +} |