diff options
| author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2016-09-09 14:08:50 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-11-01 17:31:59 +0100 |
| commit | ec7293652af797b2595bec396bae8cd625afbf8e (patch) | |
| tree | 0dd1005f1eb4212438817bc24aabe6b08f03209e /src/mainboard/google/eve/acpi | |
| parent | 25445dca1700bea7c83e6d12c7936253ef9af8ca (diff) | |
| download | coreboot-ec7293652af797b2595bec396bae8cd625afbf8e.tar.xz | |
soc/apollolake: Add soc core init
Add soc core init to set up the following feature MSRs:
1. C-states
2. IO/Mwait redirection
BUG=chrome-os-partner:56922
BRANCH=None
TEST= Check C-state functioning using 'powertop'. Check 0xE2 and
0xE4 MSR to verify IO/Mwait redirection.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I99b66b02eb790b6b348be7c964d21ec9a6926926
Reviewed-on: https://review.coreboot.org/17168
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/google/eve/acpi')
0 files changed, 0 insertions, 0 deletions