diff options
author | Duncan Laurie <dlaurie@chromium.org> | 2016-10-28 09:13:52 -0700 |
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committer | Duncan Laurie <dlaurie@chromium.org> | 2016-11-01 22:54:25 +0100 |
commit | 81485d2763f461ce28dad2ffc43441c4bae570dd (patch) | |
tree | a41429a0cf17fef0dc7520f69265708ed47ba932 /src/mainboard/google/eve/dsdt.asl | |
parent | ec7293652af797b2595bec396bae8cd625afbf8e (diff) | |
download | coreboot-81485d2763f461ce28dad2ffc43441c4bae570dd.tar.xz |
google/eve: Add new board
Add the eve board files using kabylake and FSP 2.0.
BUG=chrome-os-partner:58666
TEST=build and boot on eve board
Change-Id: I7ca71fe052608d710ee65d078df7af7b55d382bc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17177
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/google/eve/dsdt.asl')
-rw-r--r-- | src/mainboard/google/eve/dsdt.asl | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/src/mainboard/google/eve/dsdt.asl b/src/mainboard/google/eve/dsdt.asl new file mode 100644 index 0000000000..2882d50f19 --- /dev/null +++ b/src/mainboard/google/eve/dsdt.asl @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "ec.h" +#include "gpio.h" + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + /* Some generic macros */ + #include <soc/intel/skylake/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/skylake/acpi/globalnvs.asl> + + /* CPU */ + #include <soc/intel/skylake/acpi/cpu.asl> + + Scope (\_SB) + { + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + } + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + /* Chrome OS specific */ + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + /* Chipset specific sleep states */ + #include <soc/intel/skylake/acpi/sleepstates.asl> + + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } + + /* Dynamic Platform Thermal Framework */ + Scope (\_SB) + { + #include "acpi/dptf.asl" + } +} |