diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2017-02-17 17:24:12 -0800 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2017-02-20 04:29:25 +0100 |
| commit | 6c8238521eaf2216c9a41502be1cb2703a0d6f3e (patch) | |
| tree | 0e6c3cce8cda5ee415f4f203adae2e6ebac0fd42 /src/mainboard/google/eve | |
| parent | 25c7d9342b8bdee61710a516440e4b9c4b83fb09 (diff) | |
| download | coreboot-6c8238521eaf2216c9a41502be1cb2703a0d6f3e.tar.xz | |
google/eve: Fix FPC support
Currently UART0 GPIOs are being put into native mode during FSP-S
stage, so have ramstage re-configure them back to regular GPIO mode.
GPP_C8 does not seem to be functioning properly when routed to the
APIC, possibly due to the UART0 being enabled even though it is unused,
which is required because UART0 is PCI 1e.0 and so must be present for
other 1e.x functions to be enumerated. Instead, use this pin as a GPIO
interrupt so it will be routed through the GPIO controller at IRQ 14.
GPP_C9 was inverted and was only working because the pin was being
re-configured in FSP-S.
Also export the reset gpio as a device property so it can be used by
the kernel driver, which will stop it from complaining at boot.
BUG=chrome-os-partner:61233
TEST=verify that the interrupt and device is functional in the OS
Change-Id: Iaf9efbf50a13a981c6a9bbd507475777837e9c12
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18395
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/eve')
| -rw-r--r-- | src/mainboard/google/eve/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/google/eve/gpio.h | 9 | ||||
| -rw-r--r-- | src/mainboard/google/eve/mainboard.c | 4 |
3 files changed, 13 insertions, 3 deletions
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 3321565f52..dfe7281d8d 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -260,7 +260,8 @@ chip soc/intel/skylake register "hid" = "ACPI_DT_NAMESPACE_HID" register "uid" = "1" register "compat_string" = ""fpc,fpc1020"" - register "irq" = "IRQ_EDGE_LOW(GPP_C8_IRQ)" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_HIGH(GPP_C8)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C9)" device spi 0 on end end end # GSPI #1 diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h index f5b09d9bcf..85011f129a 100644 --- a/src/mainboard/google/eve/gpio.h +++ b/src/mainboard/google/eve/gpio.h @@ -103,8 +103,8 @@ static const struct pad_config gpio_table[] = { /* SML0ALERT# */ PAD_CFG_NC(GPP_C5), /* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ /* SM1DATA */ PAD_CFG_NC(GPP_C7), -/* UART0_RXD */ PAD_CFG_GPI_APIC(GPP_C8, NONE, PLTRST), /* FP_INT */ -/* UART0_TXD */ PAD_CFG_GPO(GPP_C9, 0, DEEP), /* FP_RST_ODL */ +/* UART0_RXD */ PAD_CFG_GPI(GPP_C8, NONE, PLTRST), /* FP_INT */ +/* UART0_TXD */ PAD_CFG_GPO(GPP_C9, 1, DEEP), /* FP_RST_ODL */ /* UART0_RTS# */ PAD_CFG_NC(GPP_C10), /* UART0_CTS# */ PAD_CFG_NC(GPP_C11), /* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ @@ -231,6 +231,11 @@ static const struct pad_config early_gpio_table[] = { /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ }; +static const struct pad_config late_gpio_table[] = { +/* UART0_RXD */ PAD_CFG_GPI(GPP_C8, NONE, PLTRST), /* FP_INT */ +/* UART0_TXD */ PAD_CFG_GPO(GPP_C9, 1, DEEP), /* FP_RST_ODL */ +}; + #endif #endif diff --git a/src/mainboard/google/eve/mainboard.c b/src/mainboard/google/eve/mainboard.c index bffc9e6a15..bb3c6bdb84 100644 --- a/src/mainboard/google/eve/mainboard.c +++ b/src/mainboard/google/eve/mainboard.c @@ -18,10 +18,14 @@ #include <device/device.h> #include <ec/ec.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <gpio.h> +#include <soc/gpio.h> +#include "gpio.h" static void mainboard_init(device_t dev) { mainboard_ec_init(); + gpio_configure_pads(late_gpio_table, ARRAY_SIZE(late_gpio_table)); } static void mainboard_enable(device_t dev) |