summaryrefslogtreecommitdiff
path: root/src/mainboard/google/eve
diff options
context:
space:
mode:
authorDuncan Laurie <dlaurie@google.com>2017-09-27 03:45:53 -0700
committerDuncan Laurie <dlaurie@chromium.org>2017-11-14 21:21:44 +0000
commit37da8846faa6d83c12a7f76b9c451a72805850bc (patch)
tree4e48a23949e96197c6a4e72994f3f1af25a48210 /src/mainboard/google/eve
parentd60b4930bb1493a74a1eb65b5d0a73a9483e4c4c (diff)
downloadcoreboot-37da8846faa6d83c12a7f76b9c451a72805850bc.tar.xz
mb/google/eve: Set DSP SPI clock to 12MHz
To enable faster download of hotword data set the SPI clock to the Realtek 5514 DSP chip to 12MHz instead of the default 1MHz. BUG=b:67763576, b:66161281 TEST=cras_test_client --listen /tmp/rec.raw, trigger hotword, and check the samples using hexdump or cras_test_client --playback_f /tmp/rec.raw Change-Id: I92710eae25613a8202c63888b86a269803c40fe6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org> Original-Change-Id: I7e50d755a90d739b6dec155228351c3974b2f3b9 Original-Reviewed-on: https://chromium-review.googlesource.com/686675 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Chinyue Chen <chinyue@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Tested-by: Chinyue Chen <chinyue@chromium.org> Original-Commit-Queue: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/22450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/eve')
-rw-r--r--src/mainboard/google/eve/devicetree.cb1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 3d1077b5e1..30a327e2cc 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -342,6 +342,7 @@ chip soc/intel/skylake
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "compat_string" = ""realtek,rt5514""
register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_F10_IRQ)"
+ register "speed" = "12 * MHz"
device spi 0 on end
end
end # GSPI #0