diff options
author | Subrata Banik <subrata.banik@intel.com> | 2018-05-09 14:55:09 +0530 |
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committer | Subrata Banik <subrata.banik@intel.com> | 2018-06-06 06:23:45 +0000 |
commit | c4986eb7f4eee0f305c6a6f05b45effae152062c (patch) | |
tree | 46185566d98e49bbfa60acfdedc60e1e423823d3 /src/mainboard/google/eve | |
parent | f513cebd8b966c15e3c8abcd2d0f540607ea5964 (diff) | |
download | coreboot-c4986eb7f4eee0f305c6a6f05b45effae152062c.tar.xz |
soc/intel/common/block: Add common chip config block
Adding common chip config structure which will be used to return data to
common code. When common code requires soc data, code used to fetch
entire soc config structure. With this change, common code will only get
the data/structure which is required by common code and not entire
config.
For now, adding i2c, gspi and lockdown configuration which will be used
by common code.
BUG=none
BRANCH=b:78109109
TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check
values are returned properly using common structure.
Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26189
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/eve')
-rw-r--r-- | src/mainboard/google/eve/devicetree.cb | 75 |
1 files changed, 43 insertions, 32 deletions
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index fa12d8b06d..a812c0814f 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -169,46 +169,60 @@ chip soc/intel/skylake register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| I2C0 | Touchscreen | + #| I2C1 | Early TPM access | + #| I2C2 | Touchpad | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST_PLUS, + .rise_time_ns = 98, + .fall_time_ns = 38, + }, + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 112, + .fall_time_ns = 34, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 186, + .scl_hcnt = 93, + .sda_hold = 36, + } + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 176, + .scl_hcnt = 95, + .sda_hold = 36, + } + }, + }" + # Touchscreen register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" - register "i2c[0]" = "{ - .speed = I2C_SPEED_FAST_PLUS, - .rise_time_ns = 98, - .fall_time_ns = 38, - }" # Enable I2C1 bus early for TPM access register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" - register "i2c[1]" = "{ - .early_init = 1, - .speed = I2C_SPEED_FAST, - .rise_time_ns = 112, - .fall_time_ns = 34, - }" # Touchpad register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" - register "i2c[2]" = "{ - .speed = I2C_SPEED_FAST, - .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 186, - .scl_hcnt = 93, - .sda_hold = 36, - } - }" # Audio register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" - register "i2c[4]" = "{ - .speed = I2C_SPEED_FAST, - .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 176, - .scl_hcnt = 95, - .sda_hold = 36, - } - }" # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ @@ -230,9 +244,6 @@ chip soc/intel/skylake register "tdp_pl2_override" = "15" register "tcc_offset" = "10" - # Lock Down - register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" - device cpu_cluster 0 on device lapic 0 on end end |