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| author | Duncan Laurie <dlaurie@chromium.org> | 2013-05-28 08:32:21 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-11-25 23:48:30 +0100 |
| commit | ae1ef60dfa304450bacc475cd767ac4a610a76e0 (patch) | |
| tree | 6028ba70226a3c24838836429d765e6513329ffb /src/mainboard/google/falco/romstage.c | |
| parent | 116aa3a1900dae2beb56f381e91c9890c1e8ca30 (diff) | |
| download | coreboot-ae1ef60dfa304450bacc475cd767ac4a610a76e0.tar.xz | |
falco: Update DIMM SPD table
RAM_ID indices have been changed and settled on a 2GB config
that will be the same DRAM chips but only used in one channel.
Change-Id: I444e655883ae045622ab3dfb964da4d7f86e1c0d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56810
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4198
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/google/falco/romstage.c')
| -rw-r--r-- | src/mainboard/google/falco/romstage.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/falco/romstage.c b/src/mainboard/google/falco/romstage.c index 3bf1dbd300..ef6a849391 100644 --- a/src/mainboard/google/falco/romstage.c +++ b/src/mainboard/google/falco/romstage.c @@ -91,6 +91,12 @@ static void copy_spd(struct pei_data *peid) if (spd_file->len < sizeof(peid->spd_data[0])) die("Missing SPD data."); + /* Index 0-2 are 4GB config with both CH0 and CH1 + * Index 3-5 are 2GB config with CH0 only + */ + if (spd_index > 2) + peid->dimm_channel1_disabled = 3; + memcpy(peid->spd_data[0], ((char*)CBFS_SUBHEADER(spd_file)) + spd_index * sizeof(peid->spd_data[0]), |