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authorDuncan Laurie <dlaurie@chromium.org>2013-08-09 09:11:29 -0700
committerPatrick Georgi <patrick@georgi-clan.de>2013-12-21 12:02:37 +0100
commitd538e8fb0006c4ea2d689f2d99e28f9786a6fc2e (patch)
tree11e5e832d4b6f1bcbd53e26c2443d62968fb479e /src/mainboard/google/falco
parent249a03b080be30cccecf37354b19fc8b918be447 (diff)
downloadcoreboot-d538e8fb0006c4ea2d689f2d99e28f9786a6fc2e.tar.xz
falco: Force enable ASPM on PCIe Root Port 1
Boot on falco and look in /sys/firmware/log for the string "PCIe Root Port 1 ASPM is enabled" Change-Id: Ie2111e4bb70411aa697dc63c0c11f13fbe66c8d8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65315 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4454 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/google/falco')
-rw-r--r--src/mainboard/google/falco/devicetree.cb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/falco/devicetree.cb b/src/mainboard/google/falco/devicetree.cb
index 3823ce7d92..ab8beaec2f 100644
--- a/src/mainboard/google/falco/devicetree.cb
+++ b/src/mainboard/google/falco/devicetree.cb
@@ -74,6 +74,9 @@ chip northbridge/intel/haswell
register "sio_i2c0_voltage" = "0" # 3.3V
register "sio_i2c1_voltage" = "0" # 3.3V
+ # Force enable ASPM for PCIe Port 1
+ register "pcie_port_force_aspm" = "0x01"
+
# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
register "icc_clock_disable" = "0x013e0000"