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authorDuncan Laurie <dlaurie@chromium.org>2013-10-02 14:43:58 -0700
committerPatrick Georgi <patrick@georgi-clan.de>2014-08-10 13:01:57 +0200
commitba2468d8859b7204f91c28a022b76ae995cc08a2 (patch)
tree328401c153c4fd3bda972232df577f9787fcf63d /src/mainboard/google/falco
parentb404511f13972adbeccc3c694d4f7758374a8f27 (diff)
downloadcoreboot-ba2468d8859b7204f91c28a022b76ae995cc08a2.tar.xz
falco: Add support for Samsung memory
New SPD and update to the SPD map. Add both a 4GB and 2GB option. 4GB = RAM_ID{1,1,0} 2GB = RAM_ID{1,1,1} Original-Change-Id: I37318c1b5a6ee84b7c55da00d326f10fe8af6f1e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 7eb5a4ef1062a34e883c3f356ab0dc00ba07910d) Change-Id: I0f35a7f5191fefeb5910a2d28aea153516d9a11d Reviewed-on: https://chromium-review.googlesource.com/171693 Tested-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit b02fa777aa5935021b2c69f7345dffd111cbd118) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6545 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/google/falco')
-rw-r--r--src/mainboard/google/falco/Makefile.inc14
-rw-r--r--src/mainboard/google/falco/Samsung_M471B5674QH0.spd.hex17
-rw-r--r--src/mainboard/google/falco/romstage.c8
3 files changed, 30 insertions, 9 deletions
diff --git a/src/mainboard/google/falco/Makefile.inc b/src/mainboard/google/falco/Makefile.inc
index b9a1e04f9c..043f64af65 100644
--- a/src/mainboard/google/falco/Makefile.inc
+++ b/src/mainboard/google/falco/Makefile.inc
@@ -28,12 +28,14 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
SPD_BIN = $(obj)/spd.bin
# Order of names in SPD_SOURCES is important!
-SPD_SOURCES = Micron_4KTF25664HZ # 4GB / CH0 + CH1
-SPD_SOURCES += Hynix_HMT425S6AFR6A # 4GB / CH0 + CH1
-SPD_SOURCES += Elpida_EDJ4216EFBG # 4GB / CH0 + CH1
-SPD_SOURCES += Micron_4KTF25664HZ # 2GB / CH0 only
-SPD_SOURCES += Hynix_HMT425S6AFR6A # 2GB / CH0 only
-SPD_SOURCES += Elpida_EDJ4216EFBG # 2GB / CH0 only
+SPD_SOURCES = Micron_4KTF25664HZ # 4GB / CH0 + CH1 (RAM_ID=000)
+SPD_SOURCES += Hynix_HMT425S6AFR6A # 4GB / CH0 + CH1 (RAM_ID=001)
+SPD_SOURCES += Elpida_EDJ4216EFBG # 4GB / CH0 + CH1 (RAM_ID=010)
+SPD_SOURCES += Micron_4KTF25664HZ # 2GB / CH0 only (RAM_ID=011)
+SPD_SOURCES += Hynix_HMT425S6AFR6A # 2GB / CH0 only (RAM_ID=100)
+SPD_SOURCES += Elpida_EDJ4216EFBG # 2GB / CH0 only (RAM_ID=101)
+SPD_SOURCES += Samsung_M471B5674QH0 # 4GB / CH0 + CH1 (RAM_ID=110)
+SPD_SOURCES += Samsung_M471B5674QH0 # 2GB / CH0 only (RAM_ID=111)
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
diff --git a/src/mainboard/google/falco/Samsung_M471B5674QH0.spd.hex b/src/mainboard/google/falco/Samsung_M471B5674QH0.spd.hex
new file mode 100644
index 0000000000..c2a23cdebf
--- /dev/null
+++ b/src/mainboard/google/falco/Samsung_M471B5674QH0.spd.hex
@@ -0,0 +1,17 @@
+# Samsung M471B5674QH0-YK0 (K4B4G1646Q)
+92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
+00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 01 11 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 CE 01 00 00 00 00 00 00 6C F9
+4D 34 37 31 42 35 36 37 34 51 48 30 2D 59 4B 30
+20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
diff --git a/src/mainboard/google/falco/romstage.c b/src/mainboard/google/falco/romstage.c
index 11e94fc3d8..470c1cdc57 100644
--- a/src/mainboard/google/falco/romstage.c
+++ b/src/mainboard/google/falco/romstage.c
@@ -93,11 +93,13 @@ static void copy_spd(struct pei_data *peid)
if (spd_file_len < sizeof(peid->spd_data[0]))
die("Missing SPD data.");
- /* Index 0-2 are 4GB config with both CH0 and CH1
- * Index 3-5 are 2GB config with CH0 only
+ /* Index 0-2,6 are 4GB config with both CH0 and CH1
+ * Index 3-5,7 are 2GB config with CH0 only
*/
- if (spd_index > 2)
+ switch (spd_index) {
+ case 3: case 4: case 5: case 7:
peid->dimm_channel1_disabled = 3;
+ }
memcpy(peid->spd_data[0],
spd_file +